JPS6428757A - Address converting buffer control system - Google Patents
Address converting buffer control systemInfo
- Publication number
- JPS6428757A JPS6428757A JP62183314A JP18331487A JPS6428757A JP S6428757 A JPS6428757 A JP S6428757A JP 62183314 A JP62183314 A JP 62183314A JP 18331487 A JP18331487 A JP 18331487A JP S6428757 A JPS6428757 A JP S6428757A
- Authority
- JP
- Japan
- Prior art keywords
- coincidence
- address
- rows
- memories
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To execute a proper invalidation according to a prescribed invalidating algorithm at the time of detecting a coincidence by constituting of an address converting buffer of (m) memories (m>=2) having (l) rows (l>=2) and referring to the l rows at the time of comparing with an objective real address. CONSTITUTION:In order to apply a partial purge processing to the address converting buffer 3 of m=8, l=64, the value of a logical address is stepped to 0-63 sequentially by a purge control, means to sequentially read the entries of memories 4-11, compare the real addresses of the respective entries with the real address of a comparison address register CAR in circuits 12-19 and transfer the result to a coincidence number detecting circuit 21, a coincidence row memory number holding register 24. When the number of the memories of the l rows in which the coincidence is detected is not smaller than a previously given value (n) (2<=n<=l), the whole l rows are invalidated, when it is smaller than (n), only the row in which the coincidence is detected is successively invalidated by one row. According to this constitution, a partial purge executing time and an accuracy are optimized and the overhead of a computer system can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62183314A JPH077364B2 (en) | 1987-07-24 | 1987-07-24 | Address translation buffer control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62183314A JPH077364B2 (en) | 1987-07-24 | 1987-07-24 | Address translation buffer control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6428757A true JPS6428757A (en) | 1989-01-31 |
JPH077364B2 JPH077364B2 (en) | 1995-01-30 |
Family
ID=16133528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62183314A Expired - Lifetime JPH077364B2 (en) | 1987-07-24 | 1987-07-24 | Address translation buffer control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH077364B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04101252A (en) * | 1990-08-20 | 1992-04-02 | Nec Corp | Address conversion buffer clearing system |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5680869A (en) * | 1979-12-07 | 1981-07-02 | Hitachi Ltd | Address conversion associative buffer system |
JPS56107377A (en) * | 1980-01-30 | 1981-08-26 | Fujitsu Ltd | Data processing system having partial purge tlb function |
JPS60142451A (en) * | 1983-12-29 | 1985-07-27 | Fujitsu Ltd | Address conversion control system |
JPS62197846A (en) * | 1986-02-26 | 1987-09-01 | Nec Corp | Address converting device |
JPS63269242A (en) * | 1987-04-27 | 1988-11-07 | Fujitsu Ltd | Address conversion system |
-
1987
- 1987-07-24 JP JP62183314A patent/JPH077364B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5680869A (en) * | 1979-12-07 | 1981-07-02 | Hitachi Ltd | Address conversion associative buffer system |
JPS56107377A (en) * | 1980-01-30 | 1981-08-26 | Fujitsu Ltd | Data processing system having partial purge tlb function |
JPS60142451A (en) * | 1983-12-29 | 1985-07-27 | Fujitsu Ltd | Address conversion control system |
JPS62197846A (en) * | 1986-02-26 | 1987-09-01 | Nec Corp | Address converting device |
JPS63269242A (en) * | 1987-04-27 | 1988-11-07 | Fujitsu Ltd | Address conversion system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04101252A (en) * | 1990-08-20 | 1992-04-02 | Nec Corp | Address conversion buffer clearing system |
Also Published As
Publication number | Publication date |
---|---|
JPH077364B2 (en) | 1995-01-30 |
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