JPS5599766A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS5599766A
JPS5599766A JP711079A JP711079A JPS5599766A JP S5599766 A JPS5599766 A JP S5599766A JP 711079 A JP711079 A JP 711079A JP 711079 A JP711079 A JP 711079A JP S5599766 A JPS5599766 A JP S5599766A
Authority
JP
Japan
Prior art keywords
type
region
semiconductor integrated
oxide film
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP711079A
Other languages
Japanese (ja)
Inventor
Toshinori Hirashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP711079A priority Critical patent/JPS5599766A/en
Publication of JPS5599766A publication Critical patent/JPS5599766A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233Integrated injection logic structures [I2L]
    • H01L27/0244I2L structures integrated in combination with analog structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To make it possible to operate fine processing by a method wherein a comparatively thick oxide film is formed on the low density integrated ciruit part, and the growth thickness of the oxide film is limited to a comparatively small magnitude on the high density integrated part, in a semiconductor integrated device, such as a linear IC, including an I<2>L. CONSTITUTION:A suitable donor impurity is selectively diffused into the linear circuit part and the part where the I<2>L part is to be provided, on the surface of P-type Si substrate 10, and thereby N<+>-type regions 12 and 14 are formed. After this, N<->-type Si epitaxial layer 16 is formed. Next, the surfaces of linear circuit part 16a and I<2>L part 16b are oxidized and thereby they are made into 18A and 18B. On top of these is formed anti-oxidation film 20. Next, P<+>-type isolation region 22 is formed, and it is separated into part 16A and 16B. P-type base region 24 is formed on 16A. P-type base region 26 and P-type injector region 28 are formed on 16B. Next, insulation film 30 is formed. Further, N<+>-type collector contact region 32 is formed in region 24, N<+>-type collector contact region 34 above layer 12, and a plurality of N<+>-type collector regions 36 and 38 in region 26.
JP711079A 1979-01-26 1979-01-26 Manufacture of semiconductor integrated circuit device Pending JPS5599766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP711079A JPS5599766A (en) 1979-01-26 1979-01-26 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP711079A JPS5599766A (en) 1979-01-26 1979-01-26 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5599766A true JPS5599766A (en) 1980-07-30

Family

ID=11656942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP711079A Pending JPS5599766A (en) 1979-01-26 1979-01-26 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5599766A (en)

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