JPS54124986A - Manufacure of mos field effect integratied-circuit device - Google Patents

Manufacure of mos field effect integratied-circuit device

Info

Publication number
JPS54124986A
JPS54124986A JP3328078A JP3328078A JPS54124986A JP S54124986 A JPS54124986 A JP S54124986A JP 3328078 A JP3328078 A JP 3328078A JP 3328078 A JP3328078 A JP 3328078A JP S54124986 A JPS54124986 A JP S54124986A
Authority
JP
Japan
Prior art keywords
sio
azimuth
substrate
produced
end part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3328078A
Other languages
Japanese (ja)
Inventor
Shinobu Fukunaga
Masahiko Yasuoka
Takeshi Yamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3328078A priority Critical patent/JPS54124986A/en
Publication of JPS54124986A publication Critical patent/JPS54124986A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE: To attain separation into elements making advantage of the fringe effect of an electric power flux reaching a SiO2-film end part, by improving interface level density Qss by shifting the surface azimuth of the substrate surface of the brid beak at the SiO2-film end part from its original azimuth without providing a field separate region.
CONSTITUTION: On the (100) surface of N-type Si, SiO26 and Si3N42 are formed selectively and by this mask, anisotropic etching is carried out by d3 in a mixed solution of KOH, isopropyl alcohol and water. As a result, a (111) surface high in surface level density Qss appears at an angle of Q1≈55°. Through high-temperature oxidation, thin SiO2 4a is produced on Si3N4 2 and thick SiO2 4b on substrate 1. Next, films 2, 4a and 6 are removed and B is selectively diffused to form layer 5 with d4 less than d5; and the surface of Si substrate with a surface azimuth shifted from the (100) azimuth is produced at one part of the channel of the parasitic MOSFET. Consequently, the threshold level of the parasitic MOSFET is made high and separation into elements can be realized; and thrust at the tip of the bird beak is made shallow to improve a degree of integration.
COPYRIGHT: (C)1979,JPO&Japio
JP3328078A 1978-03-22 1978-03-22 Manufacure of mos field effect integratied-circuit device Pending JPS54124986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3328078A JPS54124986A (en) 1978-03-22 1978-03-22 Manufacure of mos field effect integratied-circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3328078A JPS54124986A (en) 1978-03-22 1978-03-22 Manufacure of mos field effect integratied-circuit device

Publications (1)

Publication Number Publication Date
JPS54124986A true JPS54124986A (en) 1979-09-28

Family

ID=12382106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3328078A Pending JPS54124986A (en) 1978-03-22 1978-03-22 Manufacure of mos field effect integratied-circuit device

Country Status (1)

Country Link
JP (1) JPS54124986A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6555484B1 (en) 1997-06-19 2003-04-29 Cypress Semiconductor Corp. Method for controlling the oxidation of implanted silicon
US6579777B1 (en) * 1996-01-16 2003-06-17 Cypress Semiconductor Corp. Method of forming local oxidation with sloped silicon recess

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6579777B1 (en) * 1996-01-16 2003-06-17 Cypress Semiconductor Corp. Method of forming local oxidation with sloped silicon recess
US6555484B1 (en) 1997-06-19 2003-04-29 Cypress Semiconductor Corp. Method for controlling the oxidation of implanted silicon

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