JPS5591171A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5591171A JPS5591171A JP16304778A JP16304778A JPS5591171A JP S5591171 A JPS5591171 A JP S5591171A JP 16304778 A JP16304778 A JP 16304778A JP 16304778 A JP16304778 A JP 16304778A JP S5591171 A JPS5591171 A JP S5591171A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- volts
- region
- input signal
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
Abstract
PURPOSE:To prevent occurrence of carrier injection to a substrate when an input signal is reverse voltage even if the substrate is grounded by employing a vertical pnp-junction structure formed in an integrated circuit (IC) substrate for an input protecting circuit. CONSTITUTION:A p<->-type emitter region 20 and an n-type base region 19 are sequentially formed in a p-type collector layer 1. The region 20 is connected at 9 to the gate 6 of a MOSFET 7. A signal is applied through resistance of the region 20 from a terminal 8, and clamp voltage is applied from a terminal 22. The base region 19 is now applied with 5 volts thereto, and the collector 1 is grounded. When the input signal is lower than 5 volts, the regions 20, 19 are reversely biased, and electron is not accordingly injected into the substrate 1. When the input signal exceeds 5 volts, the transistor 21 is conducted to thus protect the input. At this time holes which are not recoupled are accelerated by the 5 volts to flow into the substrate 1. When the area of the base region 19 is increased to reduce the resistance between the base region and the substrate to the ignorable degree, positive voltage is not produced at the substrate 2. Thus, the input signal is clamped at the base potential and any higher voltage is not applied to the gate 6, thus the original input is protected without error.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16304778A JPS5591171A (en) | 1978-12-28 | 1978-12-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16304778A JPS5591171A (en) | 1978-12-28 | 1978-12-28 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5591171A true JPS5591171A (en) | 1980-07-10 |
JPS6151431B2 JPS6151431B2 (en) | 1986-11-08 |
Family
ID=15766161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16304778A Granted JPS5591171A (en) | 1978-12-28 | 1978-12-28 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5591171A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5772376A (en) * | 1980-10-24 | 1982-05-06 | Hitachi Ltd | Protective circuit device for semiconductor |
US4757363A (en) * | 1984-09-14 | 1988-07-12 | Harris Corporation | ESD protection network for IGFET circuits with SCR prevention guard rings |
JPH0239570A (en) * | 1988-07-29 | 1990-02-08 | Toshiba Corp | Input protecting circuit |
US4916085A (en) * | 1986-12-17 | 1990-04-10 | Sgs Microelettronica S.P.A. | MOS power structure with protective device against overvoltages and manufacturing process therefor |
-
1978
- 1978-12-28 JP JP16304778A patent/JPS5591171A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5772376A (en) * | 1980-10-24 | 1982-05-06 | Hitachi Ltd | Protective circuit device for semiconductor |
US4757363A (en) * | 1984-09-14 | 1988-07-12 | Harris Corporation | ESD protection network for IGFET circuits with SCR prevention guard rings |
US4916085A (en) * | 1986-12-17 | 1990-04-10 | Sgs Microelettronica S.P.A. | MOS power structure with protective device against overvoltages and manufacturing process therefor |
JPH0239570A (en) * | 1988-07-29 | 1990-02-08 | Toshiba Corp | Input protecting circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6151431B2 (en) | 1986-11-08 |
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