JPS5583902A - Sequence control circuit - Google Patents

Sequence control circuit

Info

Publication number
JPS5583902A
JPS5583902A JP15627178A JP15627178A JPS5583902A JP S5583902 A JPS5583902 A JP S5583902A JP 15627178 A JP15627178 A JP 15627178A JP 15627178 A JP15627178 A JP 15627178A JP S5583902 A JPS5583902 A JP S5583902A
Authority
JP
Japan
Prior art keywords
signal
output
reading
circuit
become
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15627178A
Other languages
Japanese (ja)
Inventor
Motohiko Kitsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OOFUJI DENKI SEISAKUSHO KK
Hashimoto Forming Industry Co Ltd
Original Assignee
OOFUJI DENKI SEISAKUSHO KK
Hashimoto Forming Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by OOFUJI DENKI SEISAKUSHO KK, Hashimoto Forming Industry Co Ltd filed Critical OOFUJI DENKI SEISAKUSHO KK
Priority to JP15627178A priority Critical patent/JPS5583902A/en
Publication of JPS5583902A publication Critical patent/JPS5583902A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To inhibit the reading in the time sector during which the decision of information is impossible by giving the delay of a fixed time to both the order reading signal and the address reading signal, thus realizing the interchange for PROM or the like.
CONSTITUTION: When synchronous signal CLK is inverted from 1W0, the signal approximating gradually to 1 with the fixed time constant is supplied to input terminal 16. Then the output of AND circuits 11 and 17 become 1 when the signal supplied to terminal 15 reaches the threshold level, and become 0 when signal CLK turns to 1 respectively. These output are then used as the address reading signals. Then the output of NOT circuit 19 becomes 0 when the synchronous signal becomes 1. In the same way, the order reading signal obtained from the output of AND circuit 26 is delayed by time T1 via the synchronous signal.
COPYRIGHT: (C)1980,JPO&Japio
JP15627178A 1978-12-20 1978-12-20 Sequence control circuit Pending JPS5583902A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15627178A JPS5583902A (en) 1978-12-20 1978-12-20 Sequence control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15627178A JPS5583902A (en) 1978-12-20 1978-12-20 Sequence control circuit

Publications (1)

Publication Number Publication Date
JPS5583902A true JPS5583902A (en) 1980-06-24

Family

ID=15624155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15627178A Pending JPS5583902A (en) 1978-12-20 1978-12-20 Sequence control circuit

Country Status (1)

Country Link
JP (1) JPS5583902A (en)

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