JPS57164493A - Read-only memory integrated circuit - Google Patents

Read-only memory integrated circuit

Info

Publication number
JPS57164493A
JPS57164493A JP4975281A JP4975281A JPS57164493A JP S57164493 A JPS57164493 A JP S57164493A JP 4975281 A JP4975281 A JP 4975281A JP 4975281 A JP4975281 A JP 4975281A JP S57164493 A JPS57164493 A JP S57164493A
Authority
JP
Japan
Prior art keywords
input
outputs
level
test
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4975281A
Other languages
Japanese (ja)
Other versions
JPS6130359B2 (en
Inventor
Makoto Mibuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4975281A priority Critical patent/JPS57164493A/en
Publication of JPS57164493A publication Critical patent/JPS57164493A/en
Publication of JPS6130359B2 publication Critical patent/JPS6130359B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To make tests in a short time without using test patterns as much as the number of addresses, by installing a controlling circuit which controls precharge and discharge signals regardless of an address input signal.
CONSTITUTION: In an address decoder 50, one of three inputs of NAND circuits 53W56 is connected to a test input terminal 3 and constitutes a controlling circuit. When such a configuration is made, the output of the circuits 53W56 can be controlled by the input of the terminal 3 irrespectively of the address input. Therefore, when the test input is high in level, an output corresponding to the input is outputted, but, when the test input is low in level, all the outputs become high level ones irrespectively of the address input. Then, only high level outputs are impressed upon N type MOSFETs 21W24 of a data storing section 20, and only low level ones are supplied to a sense section 30, and then, low level outputs are outputted from an output buffer 40. Therefore, outputs of low level can be obtained without running test patterns as much as the number of addresses.
COPYRIGHT: (C)1982,JPO&Japio
JP4975281A 1981-04-02 1981-04-02 Read-only memory integrated circuit Granted JPS57164493A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4975281A JPS57164493A (en) 1981-04-02 1981-04-02 Read-only memory integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4975281A JPS57164493A (en) 1981-04-02 1981-04-02 Read-only memory integrated circuit

Publications (2)

Publication Number Publication Date
JPS57164493A true JPS57164493A (en) 1982-10-09
JPS6130359B2 JPS6130359B2 (en) 1986-07-12

Family

ID=12839910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4975281A Granted JPS57164493A (en) 1981-04-02 1981-04-02 Read-only memory integrated circuit

Country Status (1)

Country Link
JP (1) JPS57164493A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992497A (en) * 1982-11-17 1984-05-28 Nippon Telegr & Teleph Corp <Ntt> Read-only memory device capable of detecting defect

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147924A (en) * 1975-06-13 1976-12-18 Fujitsu Ltd Memory unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992497A (en) * 1982-11-17 1984-05-28 Nippon Telegr & Teleph Corp <Ntt> Read-only memory device capable of detecting defect

Also Published As

Publication number Publication date
JPS6130359B2 (en) 1986-07-12

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