JPS558175A - Clock extraction circuit - Google Patents

Clock extraction circuit

Info

Publication number
JPS558175A
JPS558175A JP8168478A JP8168478A JPS558175A JP S558175 A JPS558175 A JP S558175A JP 8168478 A JP8168478 A JP 8168478A JP 8168478 A JP8168478 A JP 8168478A JP S558175 A JPS558175 A JP S558175A
Authority
JP
Japan
Prior art keywords
clock
modulated
extraction
wave
tcl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8168478A
Other languages
Japanese (ja)
Inventor
Ichiro Takase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8168478A priority Critical patent/JPS558175A/en
Publication of JPS558175A publication Critical patent/JPS558175A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To secure the steady extraction of the clock through a simple constitution of circuit by installing the phase detecting means as well as the shift register which delays the reception wave using the carrier extracted through the even multiplication of the reception wave as the shift clock. CONSTITUTION:Modulated wave (b) which is modulated with modulation signal (a) entered terminal 601 is branched off into two parts. And one part is delayed via shift register SR602 using doublemultiplied carrier signal (c) supplied to terminal 605 as the shift lock. Signal (d) delayed through SR602 is supplied to exclusive logic sum circuit 603 along with the otherpart of the branched modulated waves to undergo the phase change point and then extraction of clock component (e). In this case, TCL is equivalent to one cycle of the clock frequency and is set to TCL/2 for the delay time in order to give the maximum amplitude to the extracted clock. As a result, the following property can be improved to the modulated wave, thus ensuring the steady extraction of the clock.
JP8168478A 1978-07-04 1978-07-04 Clock extraction circuit Pending JPS558175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8168478A JPS558175A (en) 1978-07-04 1978-07-04 Clock extraction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8168478A JPS558175A (en) 1978-07-04 1978-07-04 Clock extraction circuit

Publications (1)

Publication Number Publication Date
JPS558175A true JPS558175A (en) 1980-01-21

Family

ID=13753174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8168478A Pending JPS558175A (en) 1978-07-04 1978-07-04 Clock extraction circuit

Country Status (1)

Country Link
JP (1) JPS558175A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0731584A2 (en) * 1995-03-02 1996-09-11 Robert Bosch Gmbh Method for transmitting digital payload

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0731584A2 (en) * 1995-03-02 1996-09-11 Robert Bosch Gmbh Method for transmitting digital payload
EP0731584A3 (en) * 1995-03-02 1996-11-06 Bosch Gmbh Robert Method for transmitting digital payload

Similar Documents

Publication Publication Date Title
JPS6467029A (en) Phase matching circuit
JPS5279862A (en) Phase synchronous device
JPS558175A (en) Clock extraction circuit
JPS5757007A (en) Orthogonal delay detecting circuit
JPS5260515A (en) Intermediate frequency phase compounding device
JPS558166A (en) Data transmission system
JPS55147060A (en) Fsk and psk modulating circuit
JPS56136041A (en) Frequency synthesizer system receiver
JPS5518136A (en) Clock extraction circuit
JPS528864A (en) Oscillator-frequency divider circuit with level shifter of electronic watch
JPS5593076A (en) Distance-measuring instrument
JPS5478653A (en) Carrier synchronous device
JPS5691552A (en) Clock signal receiving-multiplying circuit
JPS5531360A (en) Demodulator circuit
JPS52113668A (en) Modulation signal generating system
JPS5276895A (en) Automatic frequency tracking system
JPS56135281A (en) Correlation processor
JPS5394167A (en) Digital phase synchronous loop
JPS54139367A (en) Digital carrier wave extraction circuit
FR2259368A1 (en) Phase shift calculator for two signals - computes phase shifts of carrier and modulating signals
JPS57138203A (en) Digital oscillator
JPS5554483A (en) Doppler radar
JPS55149554A (en) Carrier reproducing circuit
JPS5498556A (en) Frequency multplication circuit
JPS57123785A (en) Carrier signal generating circuit