JPS558175A - Clock extraction circuit - Google Patents
Clock extraction circuitInfo
- Publication number
- JPS558175A JPS558175A JP8168478A JP8168478A JPS558175A JP S558175 A JPS558175 A JP S558175A JP 8168478 A JP8168478 A JP 8168478A JP 8168478 A JP8168478 A JP 8168478A JP S558175 A JPS558175 A JP S558175A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- modulated
- extraction
- wave
- tcl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To secure the steady extraction of the clock through a simple constitution of circuit by installing the phase detecting means as well as the shift register which delays the reception wave using the carrier extracted through the even multiplication of the reception wave as the shift clock. CONSTITUTION:Modulated wave (b) which is modulated with modulation signal (a) entered terminal 601 is branched off into two parts. And one part is delayed via shift register SR602 using doublemultiplied carrier signal (c) supplied to terminal 605 as the shift lock. Signal (d) delayed through SR602 is supplied to exclusive logic sum circuit 603 along with the otherpart of the branched modulated waves to undergo the phase change point and then extraction of clock component (e). In this case, TCL is equivalent to one cycle of the clock frequency and is set to TCL/2 for the delay time in order to give the maximum amplitude to the extracted clock. As a result, the following property can be improved to the modulated wave, thus ensuring the steady extraction of the clock.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8168478A JPS558175A (en) | 1978-07-04 | 1978-07-04 | Clock extraction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8168478A JPS558175A (en) | 1978-07-04 | 1978-07-04 | Clock extraction circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS558175A true JPS558175A (en) | 1980-01-21 |
Family
ID=13753174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8168478A Pending JPS558175A (en) | 1978-07-04 | 1978-07-04 | Clock extraction circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS558175A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0731584A2 (en) * | 1995-03-02 | 1996-09-11 | Robert Bosch Gmbh | Method for transmitting digital payload |
-
1978
- 1978-07-04 JP JP8168478A patent/JPS558175A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0731584A2 (en) * | 1995-03-02 | 1996-09-11 | Robert Bosch Gmbh | Method for transmitting digital payload |
EP0731584A3 (en) * | 1995-03-02 | 1996-11-06 | Bosch Gmbh Robert | Method for transmitting digital payload |
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