JPS5578264A - Test method for memory control circuit - Google Patents

Test method for memory control circuit

Info

Publication number
JPS5578264A
JPS5578264A JP15157178A JP15157178A JPS5578264A JP S5578264 A JPS5578264 A JP S5578264A JP 15157178 A JP15157178 A JP 15157178A JP 15157178 A JP15157178 A JP 15157178A JP S5578264 A JPS5578264 A JP S5578264A
Authority
JP
Japan
Prior art keywords
write
circuit
instruction
fed
inhibit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15157178A
Other languages
Japanese (ja)
Inventor
Shigeru Mukogasa
Yasushi Oi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15157178A priority Critical patent/JPS5578264A/en
Publication of JPS5578264A publication Critical patent/JPS5578264A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To inspect whether the write-in is inspected or not according to the write- in inhibit conditions, by knowing the change of specified address through the use of data comparison function given to normal memory test unit.
CONSTITUTION: The data delivered from the write-in data delivery section 401 is fed to the inversion circuit 501 and fed to the disagreement detection circuit as the reference data. Further, the write-in instruction delivered from the write-in instruction hold circuit 113 is fed to the discrimination circuit 112. In this case, since the write-in inhibit detection circuit 111 delivers the write-in inhibit signal to the corresponding address with the instruction from the test circuit, the discrimination circuit 112 blocks the write-in instruction delivered to the said address of memory. Thus, if the memory control circuit is not operated normally, the write-in is made and the disagreement detection circuit 31 delivers the disagreement signal to the signal line 31.
COPYRIGHT: (C)1980,JPO&Japio
JP15157178A 1978-12-07 1978-12-07 Test method for memory control circuit Pending JPS5578264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15157178A JPS5578264A (en) 1978-12-07 1978-12-07 Test method for memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15157178A JPS5578264A (en) 1978-12-07 1978-12-07 Test method for memory control circuit

Publications (1)

Publication Number Publication Date
JPS5578264A true JPS5578264A (en) 1980-06-12

Family

ID=15521427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15157178A Pending JPS5578264A (en) 1978-12-07 1978-12-07 Test method for memory control circuit

Country Status (1)

Country Link
JP (1) JPS5578264A (en)

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