JPS5457696A - Wiring inspection method - Google Patents

Wiring inspection method

Info

Publication number
JPS5457696A
JPS5457696A JP12471577A JP12471577A JPS5457696A JP S5457696 A JPS5457696 A JP S5457696A JP 12471577 A JP12471577 A JP 12471577A JP 12471577 A JP12471577 A JP 12471577A JP S5457696 A JPS5457696 A JP S5457696A
Authority
JP
Japan
Prior art keywords
wiring
address
circuit
detecting
inspection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12471577A
Other languages
Japanese (ja)
Inventor
Takeo Matsunuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12471577A priority Critical patent/JPS5457696A/en
Publication of JPS5457696A publication Critical patent/JPS5457696A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE: To enable to inspect wiring with high speed, by excluding positions to be inspected which are included in wiring group whose wiring are right from the results of inspection, from the objects of inspection in the inspection hereafter.
CONSTITUTION: Address counter circuit 8 of high speed is operated by inspection starting signal, and memory content of memory device 5 selected by the address value is sent to address detecting circuit 9 for position to be detected. When detecting position address is detected by the detecting circuit 9, address value at present is sent to address buffer circuit 10. Memory of the memory device 6 and detecting terminal of the detecting device 11 are selected by address value which is sent to the address buffer circuit 10. These outputs are compared in a comparing circuit 12, and whether there is normal wiring or miss wiring is judged. When miss wiring is existed, interruption generating circuit 13 is made to be operated, and status generating circuit 14 which divides excess wiring or un-wiring is made to be operated
COPYRIGHT: (C)1979,JPO&Japio
JP12471577A 1977-10-18 1977-10-18 Wiring inspection method Pending JPS5457696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12471577A JPS5457696A (en) 1977-10-18 1977-10-18 Wiring inspection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12471577A JPS5457696A (en) 1977-10-18 1977-10-18 Wiring inspection method

Publications (1)

Publication Number Publication Date
JPS5457696A true JPS5457696A (en) 1979-05-09

Family

ID=14892305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12471577A Pending JPS5457696A (en) 1977-10-18 1977-10-18 Wiring inspection method

Country Status (1)

Country Link
JP (1) JPS5457696A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952482U (en) * 1982-09-29 1984-04-06 富士通株式会社 cable testing equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952482U (en) * 1982-09-29 1984-04-06 富士通株式会社 cable testing equipment
JPH0213984Y2 (en) * 1982-09-29 1990-04-17

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