JPS5572034A - Preparing semiconductor element - Google Patents

Preparing semiconductor element

Info

Publication number
JPS5572034A
JPS5572034A JP14534178A JP14534178A JPS5572034A JP S5572034 A JPS5572034 A JP S5572034A JP 14534178 A JP14534178 A JP 14534178A JP 14534178 A JP14534178 A JP 14534178A JP S5572034 A JPS5572034 A JP S5572034A
Authority
JP
Japan
Prior art keywords
cut
grooves
single crystal
plates
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14534178A
Other languages
Japanese (ja)
Other versions
JPS6117148B2 (en
Inventor
Masahiro Honjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON INTERNATIONAL SEIRIYUUK
International Rectifier Corp Japan Ltd
Original Assignee
NIPPON INTERNATIONAL SEIRIYUUK
International Rectifier Corp Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON INTERNATIONAL SEIRIYUUK, International Rectifier Corp Japan Ltd filed Critical NIPPON INTERNATIONAL SEIRIYUUK
Priority to JP14534178A priority Critical patent/JPS5572034A/en
Publication of JPS5572034A publication Critical patent/JPS5572034A/en
Publication of JPS6117148B2 publication Critical patent/JPS6117148B2/ja
Granted legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode

Abstract

PURPOSE:To reduce variations in reverse peak voltage by a method wherein a semiconductor single crystal is given position mark grooves, cut into a number of thin plates, pn-junctions formed, reshaped into the original from using the mark grooves, and then cut to a required size. CONSTITUTION:A semiconductor single crystal 1, after ground to a flat surface 2 and on which two grooves 3, 4 are cut, is sliced into thin plates 5. The plate 5 is given pn-junction and the both faces are plated with ohmic metals 7. Then, using the grooves 3, 4 as positioing marks, the plates 5 are aligned in the original shape. Required number of these are selected, and plate-type brazing material 8 are inserted between the plates 5 and bonded by heating. This is then cut into checkers 8 to provide square rod-type multi-layer semiconductor rectifier elements 10. Because the element 10 is made of the nearest part of a single crystal, each pn-junction has a breakdown voltage of the closest approximation. The leads 11 are brazed to the both ends, the element is covered by silicone rubber 12, and sealed by resin 13. This structure prevents the device from local breakdown.
JP14534178A 1978-11-27 1978-11-27 Preparing semiconductor element Granted JPS5572034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14534178A JPS5572034A (en) 1978-11-27 1978-11-27 Preparing semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14534178A JPS5572034A (en) 1978-11-27 1978-11-27 Preparing semiconductor element

Publications (2)

Publication Number Publication Date
JPS5572034A true JPS5572034A (en) 1980-05-30
JPS6117148B2 JPS6117148B2 (en) 1986-05-06

Family

ID=15382929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14534178A Granted JPS5572034A (en) 1978-11-27 1978-11-27 Preparing semiconductor element

Country Status (1)

Country Link
JP (1) JPS5572034A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230747A (en) * 1982-07-30 1993-07-27 Hitachi, Ltd. Wafer having chamfered bend portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer
EP0604061A1 (en) * 1992-12-24 1994-06-29 AT&T Corp. Semiconductor fabrication
GB2307787A (en) * 1995-11-30 1997-06-04 Samsung Electronics Co Ltd Labelling semiconductor wafers
WO2008151649A1 (en) * 2007-06-13 2008-12-18 Conergy Ag Method for marking wafers

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5230747A (en) * 1982-07-30 1993-07-27 Hitachi, Ltd. Wafer having chamfered bend portions in the joint regions between the contour of the wafer and the cut-away portion of the wafer
USRE40139E1 (en) * 1982-07-30 2008-03-04 Renesas Technology Corp. Wafer having chamfered bend portions in the joint regions between the contour of the cut-away portion of the wafer
EP0604061A1 (en) * 1992-12-24 1994-06-29 AT&T Corp. Semiconductor fabrication
GB2307787A (en) * 1995-11-30 1997-06-04 Samsung Electronics Co Ltd Labelling semiconductor wafers
US5800906A (en) * 1995-11-30 1998-09-01 Samsung Electronics Co., Ltd. Label for semiconductor wafer
GB2307787B (en) * 1995-11-30 2000-10-11 Samsung Electronics Co Ltd A set of labels for a semiconductor wafer
WO2008151649A1 (en) * 2007-06-13 2008-12-18 Conergy Ag Method for marking wafers
US9640486B2 (en) 2007-06-13 2017-05-02 Conergy Ag Ingot marking for solar cell determination

Also Published As

Publication number Publication date
JPS6117148B2 (en) 1986-05-06

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