JPS5569863A - Control system for main memory unit - Google Patents

Control system for main memory unit

Info

Publication number
JPS5569863A
JPS5569863A JP14376978A JP14376978A JPS5569863A JP S5569863 A JPS5569863 A JP S5569863A JP 14376978 A JP14376978 A JP 14376978A JP 14376978 A JP14376978 A JP 14376978A JP S5569863 A JPS5569863 A JP S5569863A
Authority
JP
Japan
Prior art keywords
main memory
block
access
address
memory part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14376978A
Other languages
Japanese (ja)
Inventor
Saburo Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14376978A priority Critical patent/JPS5569863A/en
Publication of JPS5569863A publication Critical patent/JPS5569863A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To process data efficiently by dividing a main memory part into several blocks, by assigning different access period to respective blocks, and then by shortening the time of access to a block of the main memory part with a closer address.
CONSTITUTION: Main memory unit 1 consists of main memory part 3 stored with data and main memory control part 4 including a group of control circuits reading and writing data from and to main memory part 3. Main memory part 3 is divided into 1st block 5 and 2nd block 6. On arrival of an access request from CPU2, address control circuit 10 supplies the address of the access destination to distributor circuit 7 and also discriminates which of 1st block 5 and 2nd block 6 contains the access request destination according to the address, thereby generating a block discrimination signal. Then, this signal is sent to read information effective signal control circuit 9 and access control circuit 8. Consequently, access control circuit 8 generates a timing signal needed to read the result of access to the discriminated block.
COPYRIGHT: (C)1980,JPO&Japio
JP14376978A 1978-11-21 1978-11-21 Control system for main memory unit Pending JPS5569863A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14376978A JPS5569863A (en) 1978-11-21 1978-11-21 Control system for main memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14376978A JPS5569863A (en) 1978-11-21 1978-11-21 Control system for main memory unit

Publications (1)

Publication Number Publication Date
JPS5569863A true JPS5569863A (en) 1980-05-26

Family

ID=15346588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14376978A Pending JPS5569863A (en) 1978-11-21 1978-11-21 Control system for main memory unit

Country Status (1)

Country Link
JP (1) JPS5569863A (en)

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