JPS556603A - Takeover system for multiprocessor system processing - Google Patents

Takeover system for multiprocessor system processing

Info

Publication number
JPS556603A
JPS556603A JP7609978A JP7609978A JPS556603A JP S556603 A JPS556603 A JP S556603A JP 7609978 A JP7609978 A JP 7609978A JP 7609978 A JP7609978 A JP 7609978A JP S556603 A JPS556603 A JP S556603A
Authority
JP
Japan
Prior art keywords
processes
memories
control
processor
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7609978A
Other languages
Japanese (ja)
Inventor
Shigeo Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7609978A priority Critical patent/JPS556603A/en
Publication of JPS556603A publication Critical patent/JPS556603A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To execute efficiently processes while taking over processing results of respective processor units mutually under the perfect control of a control processor.
CONSTITUTION: Over access to work memory 13, conrol processor unit 12 executes the process and assigns control memories 4-1 to 4-3 which distribute processes to work processor units 3-1 to 3-3, thereby loading program modules onto corresponding memories. While attaining access to corresponding control memories, respective work processor units execute processes, but attain common memories 5 to 7 simultaneously to read operand data. When individual execution is in process, #1 interim result information, #2 interim result information, conversion end information, etc., are set onto high-speecd work memory 7. Once a series of processes end, a process end bit is set in the conversion process information, of which a corresponding unit informs unit 12.
COPYRIGHT: (C)1980,JPO&Japio
JP7609978A 1978-06-23 1978-06-23 Takeover system for multiprocessor system processing Pending JPS556603A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7609978A JPS556603A (en) 1978-06-23 1978-06-23 Takeover system for multiprocessor system processing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7609978A JPS556603A (en) 1978-06-23 1978-06-23 Takeover system for multiprocessor system processing

Publications (1)

Publication Number Publication Date
JPS556603A true JPS556603A (en) 1980-01-18

Family

ID=13595408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7609978A Pending JPS556603A (en) 1978-06-23 1978-06-23 Takeover system for multiprocessor system processing

Country Status (1)

Country Link
JP (1) JPS556603A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50113148A (en) * 1974-02-15 1975-09-05
JPS50115732A (en) * 1974-02-22 1975-09-10
JPS5267931A (en) * 1975-12-04 1977-06-06 Toshiba Corp Control system for multi-processor system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50113148A (en) * 1974-02-15 1975-09-05
JPS50115732A (en) * 1974-02-22 1975-09-10
JPS5267931A (en) * 1975-12-04 1977-06-06 Toshiba Corp Control system for multi-processor system

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