JPS5564407A - Fet gate bias circuit - Google Patents
Fet gate bias circuitInfo
- Publication number
- JPS5564407A JPS5564407A JP13787678A JP13787678A JPS5564407A JP S5564407 A JPS5564407 A JP S5564407A JP 13787678 A JP13787678 A JP 13787678A JP 13787678 A JP13787678 A JP 13787678A JP S5564407 A JPS5564407 A JP S5564407A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- capacitor
- gate
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/12—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
- H03D7/125—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes with field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
PURPOSE:To make it possible to supply the best gate bias to an apparatus with a high-frequency circuit by reversely biasing between the gate and source of FET on the basis of the output of a rectifying method of rectifying the output of a sine wave generating method. CONSTITUTION:High frequency (RF) input (f0) is applied to mixing method 1 through input capacitor C0. Local oscillating stage 2 consists of transistor Q0, etc., applied with the output of tank circuit 3, and the emitter output of transistor Q0 is positively fed back by way of a electrostatic capacity divider circuit composed of capacitors C5 and C6 so as to extract sine-wave output (fosc). Further, rectifier circuit 4 consists of capacitor C10 holding the peak value of diode D0. Mixing stage 1 consists of a tuning circuit composed of common-source N-channel depletion MOSFETM0, capacitor C8 and coil L0. To gate G of FETM0, output-V of rectifier circuit 4 is applied by way of resistance R7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13787678A JPS5564407A (en) | 1978-11-10 | 1978-11-10 | Fet gate bias circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13787678A JPS5564407A (en) | 1978-11-10 | 1978-11-10 | Fet gate bias circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5564407A true JPS5564407A (en) | 1980-05-15 |
Family
ID=15208754
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13787678A Pending JPS5564407A (en) | 1978-11-10 | 1978-11-10 | Fet gate bias circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5564407A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02126058U (en) * | 1989-03-29 | 1990-10-17 |
-
1978
- 1978-11-10 JP JP13787678A patent/JPS5564407A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02126058U (en) * | 1989-03-29 | 1990-10-17 |
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