JPS5562593A - Memory device - Google Patents

Memory device

Info

Publication number
JPS5562593A
JPS5562593A JP13343378A JP13343378A JPS5562593A JP S5562593 A JPS5562593 A JP S5562593A JP 13343378 A JP13343378 A JP 13343378A JP 13343378 A JP13343378 A JP 13343378A JP S5562593 A JPS5562593 A JP S5562593A
Authority
JP
Japan
Prior art keywords
chips
defective
regions
data
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13343378A
Other languages
Japanese (ja)
Inventor
Tokuji Furuto
Moriyuki Takamura
Shohei Ikehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13343378A priority Critical patent/JPS5562593A/en
Publication of JPS5562593A publication Critical patent/JPS5562593A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To relieve defective memory chips by substituting the defective region of a defective memory chip by the complete region of a relief memory chip.
CONSTITUTION: Defective memory chips 1W4 are so combined that defective regions may be prevented from overlapping mutually. A memory chip where regions corresponding to defective regions of chips 1W4 are complete is used as relief memory chip 5. Defect pattern information a1Wa4 corresponding to defect patterns of chips 1W4 are stored in ROM8 previously. In data write to these chips 1W5, information a1Wa4 are read out from ROM8; and when write data W.D is given to chips 1W4, some of AND gates 10W13 to which logical "1" indicating defect of information a1W a2 is given are opened, and data for defective regions is written in chip 5. Meanwhile, in data read from chips 1W5, data corresponding to defective regions of chips 1W4 are read out from corresponding regions of chip 5 on a basis of information a1Wan.
COPYRIGHT: (C)1980,JPO&Japio
JP13343378A 1978-10-30 1978-10-30 Memory device Pending JPS5562593A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13343378A JPS5562593A (en) 1978-10-30 1978-10-30 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13343378A JPS5562593A (en) 1978-10-30 1978-10-30 Memory device

Publications (1)

Publication Number Publication Date
JPS5562593A true JPS5562593A (en) 1980-05-12

Family

ID=15104652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13343378A Pending JPS5562593A (en) 1978-10-30 1978-10-30 Memory device

Country Status (1)

Country Link
JP (1) JPS5562593A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61198348A (en) * 1985-02-28 1986-09-02 Nec Corp Memory package
JPS6240700A (en) * 1985-08-17 1987-02-21 Sanyo Electric Co Ltd Semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61198348A (en) * 1985-02-28 1986-09-02 Nec Corp Memory package
JPS6240700A (en) * 1985-08-17 1987-02-21 Sanyo Electric Co Ltd Semiconductor memory

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