JPS5597085A - Bubble memory chip - Google Patents

Bubble memory chip

Info

Publication number
JPS5597085A
JPS5597085A JP361179A JP361179A JPS5597085A JP S5597085 A JPS5597085 A JP S5597085A JP 361179 A JP361179 A JP 361179A JP 361179 A JP361179 A JP 361179A JP S5597085 A JPS5597085 A JP S5597085A
Authority
JP
Japan
Prior art keywords
loop
information
defective
memory chip
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP361179A
Other languages
Japanese (ja)
Inventor
Isao Ueki
Toshihiko Watari
Tomoharu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP361179A priority Critical patent/JPS5597085A/en
Publication of JPS5597085A publication Critical patent/JPS5597085A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To omit the external memory by storing the defective loop information proper to the bubble memory chip into the bubble memory chip.
CONSTITUTION: In case plural number of minor loop 1 have some defects, the defect information is stored into paired auxiliary loop 3. The defective loop information is read out prior to the writing into minor loop 1. For instance, when the defective information of auxiliary loop #1 shows the defect, the new writing information is not supplied to the position where the corresponding information existed and with no starting given to generator 8. In case the information of auxiliary loop #2 is normal, generator 8 starts to write the new information into the corresponding position. With one circulation given along major loop 2, transfer gate 4 is opened to carry out the transfer-in action. Thus the writing equivalent to one word completes. Owing to installation of auxiliary loop 3, the peripheral circuits concerning the defective loop control can be simplified.
COPYRIGHT: (C)1980,JPO&Japio
JP361179A 1979-01-16 1979-01-16 Bubble memory chip Pending JPS5597085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP361179A JPS5597085A (en) 1979-01-16 1979-01-16 Bubble memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP361179A JPS5597085A (en) 1979-01-16 1979-01-16 Bubble memory chip

Publications (1)

Publication Number Publication Date
JPS5597085A true JPS5597085A (en) 1980-07-23

Family

ID=11562279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP361179A Pending JPS5597085A (en) 1979-01-16 1979-01-16 Bubble memory chip

Country Status (1)

Country Link
JP (1) JPS5597085A (en)

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