JPS5557955A - Testing equipment for sequence circuit - Google Patents

Testing equipment for sequence circuit

Info

Publication number
JPS5557955A
JPS5557955A JP12998278A JP12998278A JPS5557955A JP S5557955 A JPS5557955 A JP S5557955A JP 12998278 A JP12998278 A JP 12998278A JP 12998278 A JP12998278 A JP 12998278A JP S5557955 A JPS5557955 A JP S5557955A
Authority
JP
Japan
Prior art keywords
data
shift
memory circuit
circuit
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12998278A
Other languages
Japanese (ja)
Inventor
Nobuo Wakatsuki
Osamu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP12998278A priority Critical patent/JPS5557955A/en
Priority to US06/086,613 priority patent/US4317200A/en
Publication of JPS5557955A publication Critical patent/JPS5557955A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to restore a logic state, destroyed by a test, into an original state by providing a shift memory circuit stored with shift-in and shift-out start addresses and data length data, data buffers and a re-edition memory circuit.
CONSTITUTION: In accordance with a shift-in start address and data length stored in shift memory circuit 20, sequence circuit 1 which divide data into several partitions extracts test pattern data from circuit 13 to data buffer 21 by a test instruction from test pattern memory circuit 13. This data is shifted in shift register 2 and processed by external data and its result is sent to data buffer 22, where is compared with a correct value by shift-out output comparator circuit 17. In this case, since the both disagree, data in buffers 21 and 22 are edited again and stored by re- editing memory circuit 23, whose contents are inputted to buffer 21 for a reshift-in. Consequently, a logic state, destroyed by the test, can be restored into a stage before a shift-out, simplifying the pointing-out of a fault part.
COPYRIGHT: (C)1980,JPO&Japio
JP12998278A 1978-10-20 1978-10-24 Testing equipment for sequence circuit Pending JPS5557955A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP12998278A JPS5557955A (en) 1978-10-24 1978-10-24 Testing equipment for sequence circuit
US06/086,613 US4317200A (en) 1978-10-20 1979-10-19 Method and device for testing a sequential circuit divided into a plurality of partitions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12998278A JPS5557955A (en) 1978-10-24 1978-10-24 Testing equipment for sequence circuit

Publications (1)

Publication Number Publication Date
JPS5557955A true JPS5557955A (en) 1980-04-30

Family

ID=15023225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12998278A Pending JPS5557955A (en) 1978-10-20 1978-10-24 Testing equipment for sequence circuit

Country Status (1)

Country Link
JP (1) JPS5557955A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits
US4937827A (en) * 1985-03-01 1990-06-26 Mentor Graphics Corporation Circuit verification accessory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4937827A (en) * 1985-03-01 1990-06-26 Mentor Graphics Corporation Circuit verification accessory
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits

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