JPS5547525A - Data transmission method - Google Patents

Data transmission method

Info

Publication number
JPS5547525A
JPS5547525A JP11938178A JP11938178A JPS5547525A JP S5547525 A JPS5547525 A JP S5547525A JP 11938178 A JP11938178 A JP 11938178A JP 11938178 A JP11938178 A JP 11938178A JP S5547525 A JPS5547525 A JP S5547525A
Authority
JP
Japan
Prior art keywords
data
address
cdt
dxi
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11938178A
Other languages
Japanese (ja)
Other versions
JPS6016657B2 (en
Inventor
Akira Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11938178A priority Critical patent/JPS6016657B2/en
Publication of JPS5547525A publication Critical patent/JPS5547525A/en
Publication of JPS6016657B2 publication Critical patent/JPS6016657B2/en
Expired legal-status Critical Current

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Abstract

PURPOSE: To reduce load factor required for the data transmission by providing an address conversion table on the data exchange output device and outputting the data of the main memory device of CPU to CDT in accordance with the address outputted from CDT.
CONSTITUTION: The address and the address ready signal outputted from the cyclic digital information transmission device CDT1 are inputted to the data exchange output device DXI/03 which is an interface device between CDT and CPU. The microprocessor 3' incorporated in DXI/O counts the address of the data to be transmitted in the main memory device 7 by the address conversion table 4, the data is read and the data and data ready thereof are outputted to CDT. CPU can perform the data transmission without trouble in the operation processing except only that BPU6 stops only for one memory cycle when DXI/0 reads data from the main memory device 7 by DMA.
COPYRIGHT: (C)1980,JPO&Japio
JP11938178A 1978-09-29 1978-09-29 Data transfer method Expired JPS6016657B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11938178A JPS6016657B2 (en) 1978-09-29 1978-09-29 Data transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11938178A JPS6016657B2 (en) 1978-09-29 1978-09-29 Data transfer method

Publications (2)

Publication Number Publication Date
JPS5547525A true JPS5547525A (en) 1980-04-04
JPS6016657B2 JPS6016657B2 (en) 1985-04-26

Family

ID=14760093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11938178A Expired JPS6016657B2 (en) 1978-09-29 1978-09-29 Data transfer method

Country Status (1)

Country Link
JP (1) JPS6016657B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189432A (en) * 1983-04-12 1984-10-27 Fujitsu Kiden Ltd Memory storing system by direct memory access

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189432A (en) * 1983-04-12 1984-10-27 Fujitsu Kiden Ltd Memory storing system by direct memory access

Also Published As

Publication number Publication date
JPS6016657B2 (en) 1985-04-26

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