JPS5546656A - Signal mixer circuit - Google Patents

Signal mixer circuit

Info

Publication number
JPS5546656A
JPS5546656A JP12014678A JP12014678A JPS5546656A JP S5546656 A JPS5546656 A JP S5546656A JP 12014678 A JP12014678 A JP 12014678A JP 12014678 A JP12014678 A JP 12014678A JP S5546656 A JPS5546656 A JP S5546656A
Authority
JP
Japan
Prior art keywords
input terminals
signals
manufacture
supplied
mixing ratio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12014678A
Other languages
Japanese (ja)
Inventor
Junichi Yamanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12014678A priority Critical patent/JPS5546656A/en
Publication of JPS5546656A publication Critical patent/JPS5546656A/en
Pending legal-status Critical Current

Links

Landscapes

  • Studio Circuits (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE: To simplify adjustments in manufacture and maintenance processes by stabilizing operating states by varying a mixing ratio of input signals in accordance with a digital signal.
CONSTITUTION: Two input terminals 24 and 25 are provided and signals (ein1) and (ein2) are supplied from different signal sources 20 and 21 to those input terminals; and switches S1∼S8 which alternate and set input terminals 24 and 25 are provided and the output signal of each switch is supplied to input terminals 24 and 25, thereby constituting lattice-shaped resistance circuit network 26. Then, a mixing ratio of input signals (ein1) and (ein2) is varied according to a digital signal. Consequently, adjustments in manufacture and maintenance operations can be simplified in a stable operation state.
COPYRIGHT: (C)1980,JPO&Japio
JP12014678A 1978-09-29 1978-09-29 Signal mixer circuit Pending JPS5546656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12014678A JPS5546656A (en) 1978-09-29 1978-09-29 Signal mixer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12014678A JPS5546656A (en) 1978-09-29 1978-09-29 Signal mixer circuit

Publications (1)

Publication Number Publication Date
JPS5546656A true JPS5546656A (en) 1980-04-01

Family

ID=14779095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12014678A Pending JPS5546656A (en) 1978-09-29 1978-09-29 Signal mixer circuit

Country Status (1)

Country Link
JP (1) JPS5546656A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03143079A (en) * 1989-10-27 1991-06-18 Matsushita Electric Ind Co Ltd Mixing device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317736U (en) * 1976-07-27 1978-02-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317736U (en) * 1976-07-27 1978-02-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03143079A (en) * 1989-10-27 1991-06-18 Matsushita Electric Ind Co Ltd Mixing device

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