JPS554142A - Clock synchronization circuit - Google Patents

Clock synchronization circuit

Info

Publication number
JPS554142A
JPS554142A JP7695178A JP7695178A JPS554142A JP S554142 A JPS554142 A JP S554142A JP 7695178 A JP7695178 A JP 7695178A JP 7695178 A JP7695178 A JP 7695178A JP S554142 A JPS554142 A JP S554142A
Authority
JP
Japan
Prior art keywords
circuit
phase
output
pulse
jitters
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7695178A
Other languages
English (en)
Other versions
JPS5721909B2 (ja
Inventor
Koichi Minemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7695178A priority Critical patent/JPS554142A/ja
Publication of JPS554142A publication Critical patent/JPS554142A/ja
Publication of JPS5721909B2 publication Critical patent/JPS5721909B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number

Landscapes

  • Television Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP7695178A 1978-06-27 1978-06-27 Clock synchronization circuit Granted JPS554142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7695178A JPS554142A (en) 1978-06-27 1978-06-27 Clock synchronization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7695178A JPS554142A (en) 1978-06-27 1978-06-27 Clock synchronization circuit

Publications (2)

Publication Number Publication Date
JPS554142A true JPS554142A (en) 1980-01-12
JPS5721909B2 JPS5721909B2 (ja) 1982-05-10

Family

ID=13620070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7695178A Granted JPS554142A (en) 1978-06-27 1978-06-27 Clock synchronization circuit

Country Status (1)

Country Link
JP (1) JPS554142A (ja)

Also Published As

Publication number Publication date
JPS5721909B2 (ja) 1982-05-10

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