JPS554133A - Variable divider circuit - Google Patents
Variable divider circuitInfo
- Publication number
- JPS554133A JPS554133A JP7687778A JP7687778A JPS554133A JP S554133 A JPS554133 A JP S554133A JP 7687778 A JP7687778 A JP 7687778A JP 7687778 A JP7687778 A JP 7687778A JP S554133 A JPS554133 A JP S554133A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- divider
- terminal
- monostable multivibrator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/662—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by adding or suppressing pulses
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To improve greatly the S/N ratio of the output of a PLL synthesizer by controlling the operation of a phase inverter circuit at every single-counting cycle of a variable divider by using a NOR circuit, monostable multivibrator, AND circuit, FF, and OR-ELSE circuit. CONSTITUTION:To variable divider 1, an integer part of N/2 is set as a dividing ratio and a signal inputted to this divider 1 is phase-inverted by phase inverter circuit 2 and then supplied to monostable multivibrator 4 via NOR circuit 3. The output of this monostable multivibrator 4 is applied to terminal PE of divider 1 and also to one terminal of AND circuit 5, whose output is sent to terminal CL of FF6; and output Q of FF6 and the input signal are both OR-ELSE circuit 7, the output of which is applied to circuit 1. Now, the S/N ratio of a used PLL synthesizer can greatly be improved, by controlling the operation of circuit 2 at every single-counting cycle of the divider.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7687778A JPS554133A (en) | 1978-06-23 | 1978-06-23 | Variable divider circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7687778A JPS554133A (en) | 1978-06-23 | 1978-06-23 | Variable divider circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS554133A true JPS554133A (en) | 1980-01-12 |
Family
ID=13617855
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7687778A Pending JPS554133A (en) | 1978-06-23 | 1978-06-23 | Variable divider circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS554133A (en) |
-
1978
- 1978-06-23 JP JP7687778A patent/JPS554133A/en active Pending
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