JPS553641A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPS553641A
JPS553641A JP7537678A JP7537678A JPS553641A JP S553641 A JPS553641 A JP S553641A JP 7537678 A JP7537678 A JP 7537678A JP 7537678 A JP7537678 A JP 7537678A JP S553641 A JPS553641 A JP S553641A
Authority
JP
Japan
Prior art keywords
tab
bonding
lead
gold
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7537678A
Other languages
Japanese (ja)
Inventor
Hideki Kosaka
Yoshio Adachi
Hiroshi Momona
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7537678A priority Critical patent/JPS553641A/en
Publication of JPS553641A publication Critical patent/JPS553641A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent occurrence of wire-bonding defects caused by flow out of Au.Si eutectic alloy by separating a gold plated layer at the wire-bonded portion of a tab lead and a gold plated layer of a tab portion by a non-gold-plated region. CONSTITUTION:A lead frame comprises a tab portion 2 which is connectted to a semiconductor pellet, and a tab 1, and leads 3 which are radially arranged around the tab portion. Gold is plated on the tab 2, the tips of the lead to which wire bonding is made, and a portion 5 of the tab-lead 1 to which wire bonding is made, i.e. the shaded area. This lead frame is made by plating gold by the use of a mask having a portion which completely bridges the tab portion 2 and the bonding portion 5 of the tab lead in order to separate the plated layer thereof. As a result, flow out of Au.Si eutectic alloy to the plated portion 5 is prevented in the process of bonding the pellet to the tab 2, and occurrence of wire-bonding defects at the portion 5 is prevented.
JP7537678A 1978-06-23 1978-06-23 Lead frame Pending JPS553641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7537678A JPS553641A (en) 1978-06-23 1978-06-23 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7537678A JPS553641A (en) 1978-06-23 1978-06-23 Lead frame

Publications (1)

Publication Number Publication Date
JPS553641A true JPS553641A (en) 1980-01-11

Family

ID=13574414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7537678A Pending JPS553641A (en) 1978-06-23 1978-06-23 Lead frame

Country Status (1)

Country Link
JP (1) JPS553641A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727050A (en) * 1980-07-25 1982-02-13 Hitachi Ltd Lead frame and semiconductor device using said lead frame
JPS5761851U (en) * 1980-09-30 1982-04-13
JPS5827353A (en) * 1981-08-11 1983-02-18 Toshiba Corp Lead frame or semiconductor device
JPS6193654A (en) * 1984-10-15 1986-05-12 Toshiba Corp Resin sealed type semiconductor device
JPH03131043A (en) * 1989-09-21 1991-06-04 Sgs Thomson Microelectron Srl Integrated element having improved junction
US7589399B2 (en) 2005-08-26 2009-09-15 Sharp Kabushiki Kaisha Semiconductor device, lead frame used in the semiconductor device and electronic equipment using the semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5727050A (en) * 1980-07-25 1982-02-13 Hitachi Ltd Lead frame and semiconductor device using said lead frame
JPS6342859B2 (en) * 1980-07-25 1988-08-25 Hitachi Ltd
JPS5761851U (en) * 1980-09-30 1982-04-13
JPS5827353A (en) * 1981-08-11 1983-02-18 Toshiba Corp Lead frame or semiconductor device
JPS6236394B2 (en) * 1981-08-11 1987-08-06 Tokyo Shibaura Electric Co
JPS6193654A (en) * 1984-10-15 1986-05-12 Toshiba Corp Resin sealed type semiconductor device
JPH03131043A (en) * 1989-09-21 1991-06-04 Sgs Thomson Microelectron Srl Integrated element having improved junction
US7589399B2 (en) 2005-08-26 2009-09-15 Sharp Kabushiki Kaisha Semiconductor device, lead frame used in the semiconductor device and electronic equipment using the semiconductor device

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