JPS5534598A - Clock forming unit for integrated semiconductor digital circuit - Google Patents

Clock forming unit for integrated semiconductor digital circuit

Info

Publication number
JPS5534598A
JPS5534598A JP11015679A JP11015679A JPS5534598A JP S5534598 A JPS5534598 A JP S5534598A JP 11015679 A JP11015679 A JP 11015679A JP 11015679 A JP11015679 A JP 11015679A JP S5534598 A JPS5534598 A JP S5534598A
Authority
JP
Japan
Prior art keywords
forming unit
digital circuit
integrated semiconductor
clock forming
semiconductor digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11015679A
Other languages
English (en)
Inventor
Resuraa Herumuuto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPS5534598A publication Critical patent/JPS5534598A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP11015679A 1978-08-30 1979-08-29 Clock forming unit for integrated semiconductor digital circuit Pending JPS5534598A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2837882A DE2837882C2 (de) 1978-08-30 1978-08-30 Taktformer für integrierte Halbleiter-Digitalschaltungen

Publications (1)

Publication Number Publication Date
JPS5534598A true JPS5534598A (en) 1980-03-11

Family

ID=6048281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11015679A Pending JPS5534598A (en) 1978-08-30 1979-08-29 Clock forming unit for integrated semiconductor digital circuit

Country Status (5)

Country Link
US (1) US4291240A (ja)
JP (1) JPS5534598A (ja)
DE (1) DE2837882C2 (ja)
FR (1) FR2435159A1 (ja)
GB (1) GB2030404B (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4370570A (en) * 1980-11-24 1983-01-25 Dash Glen R Circuit for minimizing radiation
DE3171351D1 (en) * 1980-12-22 1985-08-14 British Telecomm Improvements in or relating to electronic clock generators
IT1210945B (it) * 1982-10-22 1989-09-29 Ates Componenti Elettron Circuito di interfaccia per generatori di segnali di sincronismo a due fasi nonsovrapposte.
DE4427015C1 (de) * 1994-07-29 1995-11-23 Siemens Ag Schaltungsanordnung zur Störsignalunterdrückung
JP2994272B2 (ja) * 1996-08-23 1999-12-27 九州日本電気株式会社 多相クロック発生回路
US6211701B1 (en) * 1996-12-16 2001-04-03 Rose Research, Llc Low power line switching circuit, device and method
US6392573B1 (en) 1997-12-31 2002-05-21 Intel Corporation Method and apparatus for reduced glitch energy in digital-to-analog converter
DE19841203C1 (de) * 1998-09-09 1999-12-16 Siemens Ag Digitale Schaltung
US6407732B1 (en) 1998-12-21 2002-06-18 Rose Research, L.L.C. Low power drivers for liquid crystal display technologies
KR100635500B1 (ko) * 2005-05-24 2006-10-17 삼성에스디아이 주식회사 시프트 레지스터 및 이를 포함하는 유기 전계발광 표시장치
KR100775219B1 (ko) * 2006-03-10 2007-11-12 엘지이노텍 주식회사 인터페이스 장치 및 인터페이스 방법
US7683655B2 (en) * 2007-01-16 2010-03-23 Atmel Automotive Gmbh Integrated circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1139541B (de) * 1961-03-28 1962-11-15 Licentia Gmbh Anordnung zur Erzeugung von gegeneinander versetzten Impulsfolgen
US3225301A (en) * 1963-06-04 1965-12-21 Control Data Corp Pulse resynchronizing system for converting asynchronous, random length data signal into data signal synchronous with clock signal
DE1228303B (de) * 1965-04-23 1966-11-10 Philips Patentverwaltung Einrichtung zur Synchronisation von Zaehlsignalen mit einer Taktpulsfrequenz
US3393367A (en) * 1965-12-08 1968-07-16 Rca Corp Circuit for generating two consecutive same-duration pulses, each on separate outputterminals, regardless of triggering-pulse duration
DE2015129A1 (de) * 1969-04-07 1970-10-15 Institut für Elektro-Anlagen, Berlin Patentwesen, Ost-Berlin WPI39039 Steuerbarer Taktgenerator für digitale informationsverarbeitende Systeme
US3624518A (en) * 1970-03-24 1971-11-30 Us Navy Single pulse switch circuit
US3825772A (en) * 1973-05-25 1974-07-23 Ibm Contact bounce eliminator circuit with low standby power
DE2345837A1 (de) * 1973-09-12 1975-03-20 Merk Gmbh Telefonbau Fried Schaltungsanordnung fuer einen mindestens zwei zueinander phasenverschobene taktfolgen gleicher frequenz liefernden elektronischen taktgenerator
DE2713319C2 (de) * 1977-03-25 1983-08-18 Siemens AG, 1000 Berlin und 8000 München Taktgeber für digitale Halbleiterschaltungen

Also Published As

Publication number Publication date
US4291240A (en) 1981-09-22
DE2837882A1 (de) 1980-03-13
FR2435159A1 (fr) 1980-03-28
GB2030404A (en) 1980-04-02
FR2435159B1 (ja) 1984-03-09
DE2837882C2 (de) 1984-03-29
GB2030404B (en) 1982-09-15

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