JPS5534565A - Timing system for pulse transmission - Google Patents

Timing system for pulse transmission

Info

Publication number
JPS5534565A
JPS5534565A JP10750178A JP10750178A JPS5534565A JP S5534565 A JPS5534565 A JP S5534565A JP 10750178 A JP10750178 A JP 10750178A JP 10750178 A JP10750178 A JP 10750178A JP S5534565 A JPS5534565 A JP S5534565A
Authority
JP
Japan
Prior art keywords
peak value
output
frequency
vcm5
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10750178A
Other languages
Japanese (ja)
Other versions
JPS576854B2 (en
Inventor
Yoshitaka Takasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10750178A priority Critical patent/JPS5534565A/en
Priority to US06/066,643 priority patent/US4320527A/en
Priority to NL7906284A priority patent/NL7906284A/en
Priority to FR7920871A priority patent/FR2435868A1/en
Priority to GB7928744A priority patent/GB2031693A/en
Priority to DE2933403A priority patent/DE2933403C3/en
Publication of JPS5534565A publication Critical patent/JPS5534565A/en
Publication of JPS576854B2 publication Critical patent/JPS576854B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/007—Detection of the synchronisation error by features other than the received signal transition detection of error based on maximum signal power, e.g. peak value, maximizing autocorrelation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain a broad frequency drawing range by using a code with the limited number of identical-polarity pulses for a self-timing system and then by controlling VCM (voltage variable multivibrator) of a frequency control loop according to the peak value of its integral waveform. CONSTITUTION:Received pulses are waveform-shaped by limiter 2-1 and then integrated by integrator 3-1. Peak detection circuit 4-1 applies the peak value of its integral waveform to comparator 6. The output of VCM5, on the other hand, is similarly passed through limiter 2-2, integrator 3-2 and peak detection circuit 4-2 to apply the peak value of its integral waveform to comparator 6. The difference in peak value between the both is equivalent to a difference in frequency between the received pulses and output pulses of VCM5. Then, the comparison output of this is passed through low-pass filter 7 to control the frequency of VCM5. Further, the output of phase comparator circuit 9 is applied to adder 8 to form a phase control loop, thereby making perfect synchronism possible.
JP10750178A 1978-08-18 1978-09-04 Timing system for pulse transmission Granted JPS5534565A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP10750178A JPS5534565A (en) 1978-09-04 1978-09-04 Timing system for pulse transmission
US06/066,643 US4320527A (en) 1978-08-18 1979-08-15 Bit synchronizing system for pulse signal transmission
NL7906284A NL7906284A (en) 1978-08-18 1979-08-17 BIT SYNCHRONIZER FOR IMPULSE SIGNAL TRANSMISSION.
FR7920871A FR2435868A1 (en) 1978-08-18 1979-08-17 BIT SYNCHRONIZATION SYSTEM FOR PULSE SIGNAL TRANSMISSION
GB7928744A GB2031693A (en) 1978-08-18 1979-08-17 Timing signal extraction system
DE2933403A DE2933403C3 (en) 1978-08-18 1979-08-17 Bit synchronization system for pulse signal transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10750178A JPS5534565A (en) 1978-09-04 1978-09-04 Timing system for pulse transmission

Publications (2)

Publication Number Publication Date
JPS5534565A true JPS5534565A (en) 1980-03-11
JPS576854B2 JPS576854B2 (en) 1982-02-06

Family

ID=14460801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10750178A Granted JPS5534565A (en) 1978-08-18 1978-09-04 Timing system for pulse transmission

Country Status (1)

Country Link
JP (1) JPS5534565A (en)

Also Published As

Publication number Publication date
JPS576854B2 (en) 1982-02-06

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