JPS5529179A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5529179A
JPS5529179A JP10316178A JP10316178A JPS5529179A JP S5529179 A JPS5529179 A JP S5529179A JP 10316178 A JP10316178 A JP 10316178A JP 10316178 A JP10316178 A JP 10316178A JP S5529179 A JPS5529179 A JP S5529179A
Authority
JP
Japan
Prior art keywords
layer
knock
mask
leakage current
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10316178A
Other languages
Japanese (ja)
Inventor
Takashi Sato
Shinichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10316178A priority Critical patent/JPS5529179A/en
Publication of JPS5529179A publication Critical patent/JPS5529179A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the leakage current of a device by employing a procedure that in forming an impurity ion injuction layer inside a semiconductor substrate by use of a selective mask, a surface layer which is knock-on by the mask and in which the impurity concentration increase is removed by etching.
CONSTITUTION: Impurity ions are injected into a Si substrate 1 by the use of a selective mask of SiO2, and then a stained layer of SiC and the like formed on the surface of an injection layer 3 is removed with a mixed boil solution of NH4OH, H2O2 and H2O. Then, a knock-on layer 4 formed at the same time is removed, but this removal is effected by slight etching utilizing a mixed solution of HF and HNO3 having a slow etching speed since the knock-on layer 4 is as thin as 100 to 300Å. In this way, the layer 4 is removed and at the same tine the thicknesses of masking layers 2 and 3 are slightly reduced. By so arranging, the leakage current of an element is markedly reduced in providing the element in the layer 3.
COPYRIGHT: (C)1980,JPO&Japio
JP10316178A 1978-08-24 1978-08-24 Semiconductor device Pending JPS5529179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10316178A JPS5529179A (en) 1978-08-24 1978-08-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10316178A JPS5529179A (en) 1978-08-24 1978-08-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5529179A true JPS5529179A (en) 1980-03-01

Family

ID=14346771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10316178A Pending JPS5529179A (en) 1978-08-24 1978-08-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5529179A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179528A (en) * 2013-03-15 2014-09-25 Mitsubishi Electric Corp Semiconductor element manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014179528A (en) * 2013-03-15 2014-09-25 Mitsubishi Electric Corp Semiconductor element manufacturing method

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