JPS5521195A - Integrated circuit module - Google Patents

Integrated circuit module

Info

Publication number
JPS5521195A
JPS5521195A JP8158579A JP8158579A JPS5521195A JP S5521195 A JPS5521195 A JP S5521195A JP 8158579 A JP8158579 A JP 8158579A JP 8158579 A JP8158579 A JP 8158579A JP S5521195 A JPS5521195 A JP S5521195A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit module
module
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8158579A
Other languages
English (en)
Other versions
JPS5826171B2 (ja
Inventor
Toomasu Makumahon Jiyu Moorisu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5521195A publication Critical patent/JPS5521195A/ja
Publication of JPS5826171B2 publication Critical patent/JPS5826171B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54Testing for continuity
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP54081585A 1978-07-31 1979-06-29 集積回路モジユ−ル Expired JPS5826171B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/929,480 US4220917A (en) 1978-07-31 1978-07-31 Test circuitry for module interconnection network

Publications (2)

Publication Number Publication Date
JPS5521195A true JPS5521195A (en) 1980-02-15
JPS5826171B2 JPS5826171B2 (ja) 1983-06-01

Family

ID=25457924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54081585A Expired JPS5826171B2 (ja) 1978-07-31 1979-06-29 集積回路モジユ−ル

Country Status (3)

Country Link
US (1) US4220917A (ja)
EP (1) EP0008002A1 (ja)
JP (1) JPS5826171B2 (ja)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612760A (en) * 1979-07-10 1981-02-07 Nec Corp Multi chip lsi package
US4411719A (en) * 1980-02-07 1983-10-25 Westinghouse Electric Corp. Apparatus and method for tape bonding and testing of integrated circuit chips
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4486705A (en) * 1981-01-16 1984-12-04 Burroughs Corporation Method of testing networks on a wafer having grounding points on its periphery
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4395767A (en) * 1981-04-20 1983-07-26 Control Data Corporation Interconnect fault detector for LSI logic chips
US4494066A (en) * 1981-07-02 1985-01-15 International Business Machines Corporation Method of electrically testing a packaging structure having n interconnected integrated circuit chips
US4504784A (en) * 1981-07-02 1985-03-12 International Business Machines Corporation Method of electrically testing a packaging structure having N interconnected integrated circuit chips
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4602271A (en) * 1981-07-22 1986-07-22 International Business Machines Corporation Personalizable masterslice substrate for semiconductor chips
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4509008A (en) * 1982-04-20 1985-04-02 International Business Machines Corporation Method of concurrently testing each of a plurality of interconnected integrated circuit chips
US4469553A (en) * 1983-06-27 1984-09-04 Electronic Packaging Co. System for manufacturing, changing, repairing, and testing printed circuit boards
US4920454A (en) * 1983-09-15 1990-04-24 Mosaic Systems, Inc. Wafer scale package system and header and method of manufacture thereof
EP0155965A4 (en) * 1983-09-15 1987-09-07 Mosaic Systems Inc DISC.
EP0174950A4 (en) * 1984-02-21 1988-02-05 Mosaic Systems Inc PACKING SYSTEM ON SEMICONDUCTOR DISC SCALE AND LADDER AND METHOD FOR PRODUCING THE SAME.
FR2567684B1 (fr) * 1984-07-10 1988-11-04 Nec Corp Module ayant un substrat ceramique multicouche et un circuit multicouche sur ce substrat et procede pour sa fabrication
JP2601792B2 (ja) * 1985-05-15 1997-04-16 株式会社東芝 大規模集積回路装置
US4703484A (en) * 1985-12-19 1987-10-27 Harris Corporation Programmable integrated circuit fault detection apparatus
US5036380A (en) * 1988-03-28 1991-07-30 Digital Equipment Corp. Burn-in pads for tab interconnects
JPH03211481A (ja) * 1990-01-17 1991-09-17 Nec Corp Lsiテスト回路
GB9212646D0 (en) * 1992-06-15 1992-07-29 Marconi Instruments Ltd A method of and equipment for testing the electrical conductivity of a connection
TW396480B (en) * 1994-12-19 2000-07-01 Matsushita Electric Ind Co Ltd Semiconductor chip and semiconductor wafer with power pads used for probing test
ATE146282T1 (de) * 1995-03-16 1996-12-15 Siemens Ag Platine mit eingebauter kontaktfühlerprüfung für integrierte schaltungen
US5736862A (en) * 1995-06-22 1998-04-07 Genrad, Inc. System for detecting faults in connections between integrated circuits and circuit board traces
US5686843A (en) * 1995-06-30 1997-11-11 International Business Machines Corporation Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module
US6079040A (en) * 1996-09-09 2000-06-20 Chips & Technologies, Inc. Module level scan testing
TW442945B (en) * 1998-11-20 2001-06-23 Sony Computer Entertainment Inc Integrated circuit chip, integrated circuit device, printed circuit board and electronic machine
JP2000286315A (ja) * 1999-03-29 2000-10-13 Sanyo Electric Co Ltd 半導体チップのパッド配置方法
US6512289B1 (en) * 2000-05-09 2003-01-28 Xilinx, Inc. Direct current regulation on integrated circuits under high current design conditions
US7132841B1 (en) * 2000-06-06 2006-11-07 International Business Machines Corporation Carrier for test, burn-in, and first level packaging
DE102004014242B4 (de) * 2004-03-24 2014-05-28 Qimonda Ag Integrierter Baustein mit mehreren voneinander getrennten Substraten
KR100843227B1 (ko) * 2007-01-08 2008-07-02 삼성전자주식회사 프로브를 이용한 반도체 메모리 장치의 테스트 방법 및 그방법을 사용하는 반도체 메모리 장치
CN102642983B (zh) * 2012-04-21 2014-03-05 余炳炎 一种应用于养殖池的水质过滤处理系统
TWI647581B (zh) * 2017-11-22 2019-01-11 緯創資通股份有限公司 電路板以及佈局結構

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4924076A (ja) * 1972-05-05 1974-03-04
JPS5120259A (ja) * 1974-07-26 1976-02-18 Dainippon Printing Co Ltd Purasuchitsukurenzunoseizoho
JPS5332679A (en) * 1976-09-08 1978-03-28 Hitachi Ltd Easy to inspect lsi mounting package

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781683A (en) * 1971-03-30 1973-12-25 Ibm Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration
US3762037A (en) * 1971-03-30 1973-10-02 Ibm Method of testing for the operability of integrated semiconductor circuits having a plurality of separable circuits
US3815025A (en) * 1971-10-18 1974-06-04 Ibm Large-scale integrated circuit testing structure
US3795973A (en) * 1971-12-15 1974-03-12 Hughes Aircraft Co Multi-level large scale integrated circuit array having standard test points
US3803483A (en) * 1972-05-05 1974-04-09 Ibm Semiconductor structure for testing of metallization networks on insulative substrates supporting semiconductor chips
GB1377859A (en) * 1972-08-03 1974-12-18 Catt I Digital integrated circuits
US3789205A (en) * 1972-09-28 1974-01-29 Ibm Method of testing mosfet planar boards
US4055754A (en) * 1975-12-22 1977-10-25 Chesley Gilman D Memory device and method of testing the same
US4140967A (en) * 1977-06-24 1979-02-20 International Business Machines Corporation Merged array PLA device, circuit, fabrication method and testing technique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4924076A (ja) * 1972-05-05 1974-03-04
JPS5120259A (ja) * 1974-07-26 1976-02-18 Dainippon Printing Co Ltd Purasuchitsukurenzunoseizoho
JPS5332679A (en) * 1976-09-08 1978-03-28 Hitachi Ltd Easy to inspect lsi mounting package

Also Published As

Publication number Publication date
EP0008002A1 (en) 1980-02-20
US4220917A (en) 1980-09-02
JPS5826171B2 (ja) 1983-06-01

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