EP0155965A4 - Wafer. - Google Patents

Wafer.

Info

Publication number
EP0155965A4
EP0155965A4 EP19850900508 EP85900508A EP0155965A4 EP 0155965 A4 EP0155965 A4 EP 0155965A4 EP 19850900508 EP19850900508 EP 19850900508 EP 85900508 A EP85900508 A EP 85900508A EP 0155965 A4 EP0155965 A4 EP 0155965A4
Authority
EP
European Patent Office
Prior art keywords
wafer
die
monolithic
sites
interconnection system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19850900508
Other languages
German (de)
French (fr)
Other versions
EP0155965A1 (en
Inventor
Herbert Stopper
Cornelius Churchill Perkins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaic Systems Inc
Original Assignee
Mosaic Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaic Systems Inc filed Critical Mosaic Systems Inc
Publication of EP0155965A1 publication Critical patent/EP0155965A1/en
Publication of EP0155965A4 publication Critical patent/EP0155965A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Definitions

  • This invention relates to a wafer, a wafer scale device, a monolithic wafer and a hybrid monolithic wafer which incorporates commercial or custom fabricated chips into complete systems made thereon, " as well as techniques of the manufacture of wafer scale devices.
  • the "chip” is the basis for many of today's advanced computer and electronic devices. However, even as the size of the chip has grown from the original integrated circuit, to a large scale integrated circuit, and to a very large scale integrated circuit, chips have always been manufactured on wafers as an intermediate step in their manufacturing process.
  • the wafer when manufactured, is made with many usually identical circuits located in die spread out across the surface of the wafer. Thereafter, these circuits are diced and the individual die become what is referred to as chips.
  • the circuits are tested on the wafer, the bad ones marked, and then the "chips" are diced and sorted for the individual good chips which are then packaged in packages such as the familiar dual in line packages- seen in many printed circuit boards today. Often the final high speed tests are only capable of being performed after the chip is in its package.
  • FIG 1 is a single drawing illustrating the preferred embodiment of our invention.
  • Figure 1 The details of Figure 1 can be understood by those skilled in the art who know that a wafer is usually a very thin cylinder of silicon on which die are deposited. Figure 1 represents a cross section of that silicon wafer
  • the metal layers can have connections which are ' formed by amorphous semiconductor material. This is by way of an 5 amorphous via, as described therein. Connections between the metal layers or between the metal layers and the substrate can be made through via holes in the insulation layer between metals or between layers respectively.
  • the real estate of the wafer is divided into special areas called cells and signal hookup areas and power hookup areas are provided.
  • the cells were intended to host integrated circuit chips in a hybrid system of chips and metal layers with the interconnections providing signal connections between the chips on the surface..
  • this application utilizes a different substrate.
  • the preferred substrate has been replaced by a silicon wafer 1 with active die incorporated on it, which die are isolated one from the other, and which each have die contact sites 2 normally used for probing during testing and for bonding during packaging.
  • a thin adhesive layer of poly mide resin insulation layer 4 To the wafer 1, and on- the upper die carrying surface, has been layered a thin adhesive layer of poly mide resin insulation layer 4.
  • This resin during the process of manufacturing the monolithic wafer, is cured and then etched to provide holes through the surface of the wafer to the die contact sites 2 so that these are uncovered temporarily.
  • the resin performs the principal task of smoothing the surface of the wafer, which is important to subsequent processing and improves step coverage. Thereafter, .
  • a thin film interconnection system 3 of which the prior interconnection system which has been incorporated by reference is a preferred example, is deposited on the insulation layer 4.
  • the interconnection system 3 has incorporated therein its own contact sites.
  • bond contact sites 5 situated at sites suitable for wire bonding.
  • probe contact sites .6 suitable for probing with a test probe 15, and there are coupling contact sites 7 suitable for coupling of the interconnection system to the underlying die at die contact site 2. While in general any contact site may be coupled to any contact site, there is a special direct connection 8 between the probe contact sites 6 and the coupling contact sites 7 for the purpose of making direct test access to the buried contact site of 7 and coupled die contact site 2.
  • wafers with isolated die formed thereon are common techniques in the intermediate process of making circuits.
  • the * wafer of the preferred embodiment is make like these wafers.
  • the interconnection system which as been described, is programmable in the manner taught by the aforementioned prior application so that interconnection can be made for signal purposes throughout any or all of the dies on the wafer, which previously had been isolated.
  • the underlying die can be a plurality of 64K or 256K RAM die, and these can be unified into a mass memory.
  • These die can be unified into a full system, which can include instruction, processor chips, I/O interfaces, and many other chips which are required to make a full system.
  • the die can be replaced if not working or unwanted by a substitute die.
  • the additional chips used to make a full system or the substitute die can be placed over the die on the wafer by adhesively bonding the downbond hybrid chips 7 carrying the desired circuits where they are placed on the surface on the interconnection system 3. Then a wire bond 11 is made to selected bonding sites, as from a site on the chip 9 to an upper bond contact site 5.
  • an upper bond contact site 5 can be used to bond an external wire bond 12 to a printed circuit board 10.
  • Stitch bonds 13 may be made between upper bonding sites 5 of the wafer. All of the interconnections of the system make the wafer into a true monolithic wafer, and when additional or substitute chips are downbonded to the surface of the wafer, we consider this a hybrid monolithic wafer system.

Abstract

A wafer (1) on which is formed a layer of thin film as an interconnection system (3) with contact sites (2, 7) between the interconnection system (3) and die bonding sites (2) of the wafer (1) to form a monolithic wafer. The interconnection system (3) has bonding sites on the surface of the wafer (1) to which chips are bonded to form a hybrid monolithic wafer system.

Description

WAFER
BACKGROUND OF THE INVENTION
This invention relates to a wafer, a wafer scale device, a monolithic wafer and a hybrid monolithic wafer which incorporates commercial or custom fabricated chips into complete systems made thereon, "as well as techniques of the manufacture of wafer scale devices.
The "chip" is the basis for many of today's advanced computer and electronic devices. However, even as the size of the chip has grown from the original integrated circuit, to a large scale integrated circuit, and to a very large scale integrated circuit, chips have always been manufactured on wafers as an intermediate step in their manufacturing process. The wafer, when manufactured, is made with many usually identical circuits located in die spread out across the surface of the wafer. Thereafter, these circuits are diced and the individual die become what is referred to as chips. In order to get good circuits, the circuits are tested on the wafer, the bad ones marked, and then the "chips" are diced and sorted for the individual good chips which are then packaged in packages such as the familiar dual in line packages- seen in many printed circuit boards today. Often the final high speed tests are only capable of being performed after the chip is in its package. SUMMARY OF THE INVENTION
In contrast to this present state of the art, we have been-working on a new level of technology, which we call wafer scale integration. This technology utilizes the entire wafer to make a system package, as opposed to a chip package. To understand the technology, a gates, diodes, resistors and other well known electrical elements are fundamental units of a circuit, and a circuit in turn is a sub-element of a die, and the die or "chip" is a sub-element of a wafer. The wafer itself, in a version of our monolithic* wafer, is composed of a plurality of circuits" and is capable of being an entire system. This system is of a scale much greater than the systems _ made on single chips for the first time approximately a decade ago. Chips during the last decade have been made which have an on board memory, an instruction processor and interconnection bus to the outside world.
By utilizing available VLSI technology and our wafer scale integration techniques, we can reduce a room size mainframe computer to a single monolithic wafer. The dicing techniques can be eliminated. In addition, we have devised methods and techniques to combine circuits which are not made on a single wafer into a single unitized wafer. These devices are not merely improvements . to the state of the art, but raise much of the technology to a new level. To understand the invention, reference can be had to a single drawing, which with reference of U.S.S.N. 225,581 filed January 16, 1981, and published under WO 82/02640 of the 5th day of August 1982, which reference shall be deemed incorporated herein in its entirety. In the drawings here:
Figure 1, is a single drawing illustrating the preferred embodiment of our invention.
The details of Figure 1 can be understood by those skilled in the art who know that a wafer is usually a very thin cylinder of silicon on which die are deposited. Figure 1 represents a cross section of that silicon wafer
10 and of the other items we use and which we shall describe.
In U.S. Application No. 225,581 incorporated herein by reference there was disclosed a wafer substrated for integrated circuits which by itself may be made either of -*--* conductive or non-conductive material. ϊhis substrate, in the present invention, references the base monolithic wafer. On this substrate of the prior invention, were carried two planes or layers of patterned metal, thus providing two layers of interconnection. This patterned
20 metal is considered to be an interconnection system within the meaning of this application. In the prior application, as no known from that application, the metal layers can have connections which are' formed by amorphous semiconductor material. This is by way of an 5 amorphous via, as described therein. Connections between the metal layers or between the metal layers and the substrate can be made through via holes in the insulation layer between metals or between layers respectively. In this prior application, and in the presently preferred 0 embodiment, the real estate of the wafer is divided into special areas called cells and signal hookup areas and power hookup areas are provided. In the prior application, it was -disclosed that the cells were intended to host integrated circuit chips in a hybrid system of chips and metal layers with the interconnections providing signal connections between the chips on the surface..
Unlike the prior application, this application utilizes a different substrate. The preferred substrate has been replaced by a silicon wafer 1 with active die incorporated on it, which die are isolated one from the other, and which each have die contact sites 2 normally used for probing during testing and for bonding during packaging. To the wafer 1, and on- the upper die carrying surface, has been layered a thin adhesive layer of poly mide resin insulation layer 4. This resin, during the process of manufacturing the monolithic wafer, is cured and then etched to provide holes through the surface of the wafer to the die contact sites 2 so that these are uncovered temporarily. The resin performs the principal task of smoothing the surface of the wafer, which is important to subsequent processing and improves step coverage. Thereafter, . during the process of manufacture of the monolithic wafer a thin film interconnection system 3, of which the prior interconnection system which has been incorporated by reference is a preferred example, is deposited on the insulation layer 4. The interconnection system 3 has incorporated therein its own contact sites. On the upper surface are bond contact sites 5, situated at sites suitable for wire bonding. There are probe contact sites .6 suitable for probing with a test probe 15, and there are coupling contact sites 7 suitable for coupling of the interconnection system to the underlying die at die contact site 2. While in general any contact site may be coupled to any contact site, there is a special direct connection 8 between the probe contact sites 6 and the coupling contact sites 7 for the purpose of making direct test access to the buried contact site of 7 and coupled die contact site 2.
Here is to be noted that wafers with isolated die formed thereon are common techniques in the intermediate process of making circuits. The* wafer of the preferred embodiment is make like these wafers. The interconnection system which as been described, is programmable in the manner taught by the aforementioned prior application so that interconnection can be made for signal purposes throughout any or all of the dies on the wafer, which previously had been isolated. The underlying die can be a plurality of 64K or 256K RAM die, and these can be unified into a mass memory.
These die can be unified into a full system, which can include instruction, processor chips, I/O interfaces, and many other chips which are required to make a full system. The die can be replaced if not working or unwanted by a substitute die. The additional chips used to make a full system or the substitute die can be placed over the die on the wafer by adhesively bonding the downbond hybrid chips 7 carrying the desired circuits where they are placed on the surface on the interconnection system 3. Then a wire bond 11 is made to selected bonding sites, as from a site on the chip 9 to an upper bond contact site 5. Similarly, an upper bond contact site 5 can be used to bond an external wire bond 12 to a printed circuit board 10. Stitch bonds 13 may be made between upper bonding sites 5 of the wafer. All of the interconnections of the system make the wafer into a true monolithic wafer, and when additional or substitute chips are downbonded to the surface of the wafer, we consider this a hybrid monolithic wafer system.

Claims

What is claimed is:
1. A monolithic wafer comprising, a silicon wafer having a plurality of active die formed thereon in the form of isolated die, said die having test and bonding die contact sites, an interconnection system deposited on the wafer which has coupling sites for coupling the interconnection system to said die contact sites.
2. A monolithic wafer according to claim 1, including programmable means within the interconnection system for coupling selected contact sites of one die to selected contact sites of another die on said wafer.
3. A monolithic wafer according to claim 1 wherein there are downbonded chips coupled to the interconnection system physically bonded to the interconnection system and electrically coupled through the interconnection system to other chips or die of the monolithic wafer to form a complete system.
4. A monolithic wafer according to claim 1 wherein there are bonding contact sites and probe contact sites on the surface of the wafer.
5. A monolithic wafer according to claim 1 wherein there is a probe contact site on the surface of the wafer which is connected through the system to a coupling contact site beneath the surface of the wafer, which coupling contact site is coupled to contact site of said die.
6. A monolithic wafer according to claim 1 where there are a plurality of bonding contact sites on the surface of the wafer and two or more- of the bonding sites are interconnected by an electrical switch connection.
7. A monolithic wafer according to claim 1 wherein there are external circuit connection leads from a bonding contact site of the interconnection system to a circuit board external to the monolithic wafer.
EP19850900508 1983-09-15 1984-09-12 Wafer. Withdrawn EP0155965A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53239183A 1983-09-15 1983-09-15
US532391 1983-09-15

Publications (2)

Publication Number Publication Date
EP0155965A1 EP0155965A1 (en) 1985-10-02
EP0155965A4 true EP0155965A4 (en) 1987-09-07

Family

ID=24121588

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19850900508 Withdrawn EP0155965A4 (en) 1983-09-15 1984-09-12 Wafer.

Country Status (3)

Country Link
EP (1) EP0155965A4 (en)
JP (1) JPS60502234A (en)
WO (1) WO1985001390A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2588696B1 (en) * 1985-10-16 1988-10-07 Thomson Csf HYBRID CIRCUIT AND METHOD FOR MANUFACTURING SUCH A CIRCUIT
DE4108154A1 (en) * 1991-03-14 1992-09-17 Telefunken Electronic Gmbh ELECTRONIC ASSEMBLY AND METHOD FOR PRODUCING ELECTRONIC ASSEMBLIES

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1236401A (en) * 1967-05-23 1971-06-23 Ibm Improvements relating to semiconductor structures and fabrication thereof
WO1982002603A1 (en) * 1981-01-16 1982-08-05 Robert Royce Johnson Wafer and method of testing networks thereon
WO1982002640A1 (en) * 1981-01-16 1982-08-05 Robert Royce Johnson Universal interconnection substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3699543A (en) * 1968-11-04 1972-10-17 Energy Conversion Devices Inc Combination film deposited switch unit and integrated circuits
US3795973A (en) * 1971-12-15 1974-03-12 Hughes Aircraft Co Multi-level large scale integrated circuit array having standard test points
US4206470A (en) * 1977-09-01 1980-06-03 Honeywell Inc. Thin film interconnect for multicolor IR/CCD
US4220917A (en) * 1978-07-31 1980-09-02 International Business Machines Corporation Test circuitry for module interconnection network
US4467400A (en) * 1981-01-16 1984-08-21 Burroughs Corporation Wafer scale integrated circuit
US4458297A (en) * 1981-01-16 1984-07-03 Mosaic Systems, Inc. Universal interconnection substrate
US4424579A (en) * 1981-02-23 1984-01-03 Burroughs Corporation Mask programmable read-only memory stacked above a semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1236401A (en) * 1967-05-23 1971-06-23 Ibm Improvements relating to semiconductor structures and fabrication thereof
WO1982002603A1 (en) * 1981-01-16 1982-08-05 Robert Royce Johnson Wafer and method of testing networks thereon
WO1982002640A1 (en) * 1981-01-16 1982-08-05 Robert Royce Johnson Universal interconnection substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO8501390A1 *
WIRELESS WORLD, vol. 87, no. 1546, July 1981, pages 57-59, Sheepen Place, Colchester, GB; I. CATT: "Wafer-scale integration" *

Also Published As

Publication number Publication date
EP0155965A1 (en) 1985-10-02
JPS60502234A (en) 1985-12-19
WO1985001390A1 (en) 1985-03-28

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Legal Events

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PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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17P Request for examination filed

Effective date: 19850426

AK Designated contracting states

Designated state(s): BE DE FR GB NL

A4 Supplementary search report drawn up and despatched

Effective date: 19870907

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19870924

RIN1 Information on inventor provided before grant (corrected)

Inventor name: PERKINS, CORNELIUS, CHURCHILL

Inventor name: STOPPER, HERBERT