JPH04207051A - Manufacture of wafer scale integration device - Google Patents

Abstract

PURPOSE:To enhance the efficiency of manufacturing work by forming a plurality of element chips and a signal wiring which forms a communication path between the chips, then including a process which tests the communication path between adjacent element chips prior to conducting a functional test. CONSTITUTION:A wafer 2 is provided where a signal wiring, which interconnects element chips 3 and adjacent chips 3, is formed on the wafer 2. Then, with specific attention given to the element chip 3D, power source voltage is applied to the element chips 3E and 3H which adjoin the element chip 3D vertically and horizontally as illustrated by way of probes 16 to 20 for the power source Vc and probes 21 to 25 for power source Vss. At the same time, functional testing about the element chips 3D to 3H is carried out by way of a signal probe. Then, the mutual communication pass between the element chips 3D to 3H is tested. If there exists any defect about the communication path, such defective path is excluded as a defective part at this point of time.

Description

[Detailed Description of the Invention] [Summary] The purpose of the present invention is to prevent waste in the manufacturing process from being caused by defects in communication paths and to improve the efficiency of manufacturing operations regarding wafer scale integration devices. , After forming multiple element chips and signal wiring that serves as a communication path between them on a wafer, before performing a functional test,
Tests the communication path between adjacent element chips.

[Industrial Application Field] The present invention relates to a method for manufacturing a so-called wafer scale integration device (hereinafter referred to as ws'r), which is configured by integrating circuits in the entire area of a wafer as one device.

[Prior Art] Conventionally, a WSI has been proposed as shown in FIG. 2, a schematic plan view of which is shown, and FIG. 3 showing electrical internal connections of signal wiring.

This WSI is an example of wafer scale memory, and the second
In the figure, 1 is a board, 2 is a wafer bonded to board 1, 3 is an element chip arranged on wafer 2, and 4 is a terminal for a Vcc power supply (for example, +5 [V] power supply) formed on board 1. , 5 is a terminal for Vss power supply (for example, ground), 6 is a wire for power supply, 7 is a terminal for input signal, 8 is wire for input signal, 9 is terminal for output signal, 10 is for output signal The wire 11 is a connector, and this WS
I is intended to supply power to each element chip 3 via the wire 6.

Here, as shown in FIG. 3, each element chip 3 includes a DRAM 12 as a main functional circuit section which is to perform the main function of the element chip 3, and a DRAM 12 for reconfiguring the element chip 3, that is, configuring a communication path. An element chip reconfiguration circuit section provided along with the DRAM 12, a so-called configuration logic (Configuration Log
ic (hereinafter referred to as Conlog) 13.

Each Conlog 3 has four adjacent Conlogs.
It is connected to GL B by a signal wiring 14, and is configured so that it can be connected to any one of the four adjacent Conlogs 3 by switch control in response to a mutual connection command signal supplied from the outside. For example, a bidirectional communication path 15 as shown by double lines in FIG. 3 is formed. This communication path 15 is formed while testing which of the four adjacent Conlogs 3 is normal.

Note that XMIT is an input line and RECV is an output line.

Conlogl 3 also includes a DRAM interface section, and is configured to be able to operate the DRAM via this DRAM interface section.

Such a WSI has conventionally been manufactured as shown in FIGS. 4A to 4C.

That is, first, as shown in FIG. 4A, a wafer 2 is prepared, and signal wiring 14 (not shown in FIG. 4A) for interconnecting element chips 3 and adjacent element chips 3 is provided on this wafer 2. (see FIG. 3), followed by a DRAM 12 (not shown in FIG. 4A).

(See Figure 3).

Next, as shown in FIG. 4B, this wafer 2 is placed on the board 1.
A wire 6 for power supply is bonded to the substrate, and then a bidirectional communication path 15 is formed as shown in FIG. 4C. Here you can get WSI.

[Problems to be Solved by the Invention] For example, as shown in FIG. 5, an element chip 3A formed on the board 1 to which the input signal terminal 7 and the output signal terminal 9 are connected is If it is not possible to connect to either the element chip 3B on the upper side of the figure or the element chip 3C on the left side of the figure due to a defect in the communication path, this WSI
However, in the conventional WSI manufacturing method shown in FIG.
It can only be known in the process of forming the communication path 15,
Therefore, in a case like the example in FIG. 5, the wafer 2 is transferred to the board 1.
There was a problem in that the process of bonding the power supply wire 6 and the board 1 was completely wasted.

In view of this, an object of the present invention is to provide a WSI manufacturing method that can prevent waste in the manufacturing process due to defects in the communication path and improve the efficiency of manufacturing work. do.

[Means for Solving the Problems] In the WSI manufacturing method according to the present invention, after forming a plurality of element chips and signal wiring serving as a communication path between them on a wafer, and before performing a functional test, Its feature is that it tests the communication path between adjacent element chips.

[Operation] According to the present invention, the communication path between adjacent element chips is tested before performing the functional test, so if there is a defect in the communication path and therefore the wafer cannot be used, the defective wafer is evaluated at this point. It can be rejected as a non-defective product, and there is no need to perform wasteful steps as in the conventional example.

[Embodiment] An embodiment of the present invention will be described below with reference to FIG.

This embodiment is similar to the conventional WSI manufacturing method shown in FIG.
An example of manufacturing a WSI is shown in FIG. 2, whose schematic plan view is shown, and FIG. 3 shows the electrical internal connections of signal wiring. Therefore, in FIG. 1, FIG.
Components corresponding to those in FIG. 4 are given the same reference numerals.

In this embodiment, first, as shown in FIG. 1A, a wafer 2 is prepared, and element chips 3 and adjacent element chips 3 are connected to this wafer 2 in the same manner as shown in FIG. 4A. A signal wiring 14 (not shown in FIG. 1A, see FIG. 3) is formed.

Next, as shown in FIG. 1B, focusing on the element chip 3D, this element chip 3D and this element chip 3D are shown in the figure as follows.
Power supply voltage is supplied to the element chips 3E to 3H that are adjacent to each other in the vertical and horizontal directions through the probes 16 to 20 for Vcc power supply and the probes 21 to 25 for Vss power supply, and also through the probe for signal (not shown). Function tests were performed on element chips 3D to 3H, and then element chip 3
Mutual communication path between D to 3H (signal wiring and Conl
og) test. This is done for all the element chips 3 on the wafer 2.

Next, as shown in FIG. 1C, the wafer 2 that has passed the test is
is adhered to the board 1, a power supply wire 6 is bonded, and then a bidirectional communication path 15 is formed as shown in the first diagram. Here you can get wsr.

In this embodiment, the communication path is tested before bonding the wafer 2 to the board 1, so if a wafer has a defect in the communication path and cannot be used due to this, it is treated as a defective product at this point. the step of gluing the wafer 2 to the board 1, which is completely wasteful in this case;
There is no need to perform a bonding process for the power supply wire 6, and the board 1 is not wasted.

Therefore, according to this embodiment, it is possible to prevent wastage of the manufacturing process and the board 1 due to defects in the communication path, and it is possible to improve the efficiency of manufacturing work and the yield. .

In the above embodiment, the present invention is applied to the manufacture of a wafer scale memory that includes DRAM and Conlog during WSI, but the present invention also applies to manufacturing of a wafer scale memory that includes DRAM and Conlog as elements. It can be applied to the manufacture of all WSIs configured to reconfigure element chips using Conlog, such as wafer scale processors as elements.

[Effects of the Invention] According to the present invention, by testing the communication path between adjacent element chips before performing a functional test,
Wafers that have a defect in the communication path and are therefore unusable can be removed as defective at this point.
Since there is no need to perform unnecessary steps as in the conventional example, it is possible to improve the efficiency of manufacturing operations.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a method for manufacturing a wafer scale integration device (wsB) according to the present invention. FIG. 2 is a schematic plan view showing an example of WSI. FIG. FIG. 4 is a diagram showing the electrical internal connection of signal wiring, FIG. 4 is a diagram showing a conventional WSI manufacturing method, and FIG. 1...Board 2...Wafer 3...Element chip 4...Terminal 5 for Vcc power supply...Terminal 6 for Vss power supply...Wire for power supply 7...Input signal Terminal 8 for input signal...Wire 9 for input signal...Terminal 10 for output signal...Wire 12 for output signal...DRAM 13---ConIog 14...Signal wiring 15... Communication path Fig. 1 A schematic plan view showing an example of WSI Fig. 2 □ Communication path Fig. 2 A diagram showing electrical internal connections of signal wiring in the example WSI Fig. 3 (B) Manufacturing of conventional WSI Figure 4 showing the method

Claims (2)

[Claims] (1) After forming a plurality of element chips and signal wiring serving as a communication path between them on a wafer, the process includes testing the communication path between adjacent element chips before performing a functional test. A method for manufacturing a wafer scale integration device, characterized by: (2) An element chip having a main functional circuit section that performs the main function of the element chip and an element chip reconfiguration circuit section for reconfiguring the element chip, and element chip reconfiguration of the adjacent element chip on the wafer. After forming the signal wiring that interconnects the constituent circuit parts, this wafer is fixed to a board, and the power supply lines that should be commonly wired to each element chip are formed, and the element chips are connected by interconnection command signals. Before forming a two-way communication path via the reconfiguration circuit, supply voltage to adjacent element chips via the probe, and establish communication between the signal wiring and the element chip reconfiguration circuit. A method for manufacturing a wafer scale integration device, the method comprising the step of testing a route.