JPS55166336A - D/a converter - Google Patents

Abstract

PURPOSE:To simplify the constitution of D/A converter, by forming the circuit with the reversible counter to count the digital input signals, the FF to give the indication to the addition and subtraction actions of the counter and the smoothing circuit to smooth the output of the FF each. CONSTITUTION:Reversible counter 60 counts clock signals F2 when the output of FF7C is in the H level, and then delivers carry signal signal CR when its counting value reaches set value M. With generation of signal OR, output Q of FF70 is inverter to the L level. At the same time, counter 60 reads in digital output N of reversible counter 30 at that moment and signal CR is discontinued. With the level inversion of output Q of FF70, counter 60 begins the subtraction from counting value N, and signal CR is produced when the counting value lowers down to set value 0. Thus counter 60 reads in value N to carry out the addition. Switching circuit 80 gives the phase inversion to signal Q and then generates output P having the waveheight value used as reference voltage V0. Output P is then smoothed via smoothing circuit 90, and comparison voltage Vr is produced. Accordingly, voltage Vr is turned into the analog voltage corresponding to input digital signal N.