JPS55160390A - Driving method of dynamic memory cell - Google Patents

Driving method of dynamic memory cell

Info

Publication number
JPS55160390A
JPS55160390A JP6658779A JP6658779A JPS55160390A JP S55160390 A JPS55160390 A JP S55160390A JP 6658779 A JP6658779 A JP 6658779A JP 6658779 A JP6658779 A JP 6658779A JP S55160390 A JPS55160390 A JP S55160390A
Authority
JP
Japan
Prior art keywords
gate
capacitor
level
memory cell
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6658779A
Other languages
Japanese (ja)
Inventor
Toshio Takeshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6658779A priority Critical patent/JPS55160390A/en
Publication of JPS55160390A publication Critical patent/JPS55160390A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To make it possible to attain access to information in a memory cell efficiently by making the potential of a word line, applied to the selective gate of the memory cell, different between read and write operations. CONSTITUTION:Near intersections between word lines 3 and 4, and bit lines 1 and 2, memory cells 5 and 6 are arranged which consists of capacitor CS and selective gate GT. Then, a signal applied to gate GT when a word line is selected is provided with two levels. Namely, the 1st level is set to a potential at which gate GT is unconductive when information stored in capacitor CS is read out, and the 2nd level to the potential of the bit line and that of capacitor CS at which gate GT conducts completely. In read operation, the 1st level is used and the 2nd level is also used for write operation to eliminate the waste of bit line capacitor CB, so that access to information in a cell can be attained with efficiency.
JP6658779A 1979-05-29 1979-05-29 Driving method of dynamic memory cell Pending JPS55160390A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6658779A JPS55160390A (en) 1979-05-29 1979-05-29 Driving method of dynamic memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6658779A JPS55160390A (en) 1979-05-29 1979-05-29 Driving method of dynamic memory cell

Publications (1)

Publication Number Publication Date
JPS55160390A true JPS55160390A (en) 1980-12-13

Family

ID=13320213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6658779A Pending JPS55160390A (en) 1979-05-29 1979-05-29 Driving method of dynamic memory cell

Country Status (1)

Country Link
JP (1) JPS55160390A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4751683A (en) * 1984-10-22 1988-06-14 Mitsubishi Denki Kabushiki Kaisha Static semiconductor memory device comprising word lines each operating at three different voltage levels

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269240A (en) * 1975-12-03 1977-06-08 Ibm Semiconductor memory system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269240A (en) * 1975-12-03 1977-06-08 Ibm Semiconductor memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4751683A (en) * 1984-10-22 1988-06-14 Mitsubishi Denki Kabushiki Kaisha Static semiconductor memory device comprising word lines each operating at three different voltage levels

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