JPS55159673A - Vertical synchronizing circuit - Google Patents
Vertical synchronizing circuitInfo
- Publication number
- JPS55159673A JPS55159673A JP6801779A JP6801779A JPS55159673A JP S55159673 A JPS55159673 A JP S55159673A JP 6801779 A JP6801779 A JP 6801779A JP 6801779 A JP6801779 A JP 6801779A JP S55159673 A JPS55159673 A JP S55159673A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- vertical synchronizing
- pulse width
- vertical
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
- H04N5/10—Separation of line synchronising signal from frame synchronising signal or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Abstract
PURPOSE:To make easy the integration and to make unnecessary the adjustment of vertical oscillator at all, by making pulse signal through separation and picking up of the composite vertical synchronizing signal in composite video signals and digitizing all the vertical synchronizing circuits. CONSTITUTION:The pulse width picking up the composite synchronizing signal in the composite video signals is extended at the pulse width extension circuit 13, and the signal of a given pulse width is detected from the signal in pulse width extension with the pulse width detection circuit 14. The preiod of the specified width detection signal detected by the circuit 14 is detected at a given clock and the continuity is detected, and when specified conditions are satisfied, the vertical synchronizing detection signal is output from the continuity detection circuit 18. Further, the clock is counted for one vertical period at the vertical counter 20, and the phase between the timing signal produced at a given phase of the counter 20 and the detection signal from the circuit 18 is compared at the mode detection circuits 26,27 to judge the vertical synchronizing mode. Further, when the vertical synchronizing signal is not obtained for a given period, the operating mode of the circuits 13,14 is simultaneously switched.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6801779A JPS55159673A (en) | 1979-05-31 | 1979-05-31 | Vertical synchronizing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6801779A JPS55159673A (en) | 1979-05-31 | 1979-05-31 | Vertical synchronizing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55159673A true JPS55159673A (en) | 1980-12-11 |
JPS612343B2 JPS612343B2 (en) | 1986-01-24 |
Family
ID=13361629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6801779A Granted JPS55159673A (en) | 1979-05-31 | 1979-05-31 | Vertical synchronizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55159673A (en) |
-
1979
- 1979-05-31 JP JP6801779A patent/JPS55159673A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS612343B2 (en) | 1986-01-24 |
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