JPS55150188A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS55150188A
JPS55150188A JP5724979A JP5724979A JPS55150188A JP S55150188 A JPS55150188 A JP S55150188A JP 5724979 A JP5724979 A JP 5724979A JP 5724979 A JP5724979 A JP 5724979A JP S55150188 A JPS55150188 A JP S55150188A
Authority
JP
Japan
Prior art keywords
transistors
digit lines
sense amplifier
unselected
turning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5724979A
Other languages
Japanese (ja)
Other versions
JPS6236307B2 (en
Inventor
Kazuo Tokushige
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5724979A priority Critical patent/JPS55150188A/en
Publication of JPS55150188A publication Critical patent/JPS55150188A/en
Publication of JPS6236307B2 publication Critical patent/JPS6236307B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To realize high-speed operation with malfunction prevented by interposing transistors between a sense amplifier and digit lines, and by turning ON transistors connected to selected digit lines while turning OFF transistors connected to unselected digit lines. CONSTITUTION:As for a static memory, digit lines D and D' are connected to a couple of input and output points of memory C and also led to differential sense amplifier SA, composed of transistors Q1-Q3, via tranistors Q4 and Q5. Drains of transistors Q1 and Q2 are connected to read bus lines RB and RB'. Enable transistor Q3, and transistors Q4 and Q5 of the sense amplifier are supplied with the output of Y decoder 4'. Transistors Q4 and Q5 conduct when digit lines D and D' are selected and turn OFF when unselected. Therefore high-speed operation is carried out without any malfunction.
JP5724979A 1979-05-10 1979-05-10 Memory circuit Granted JPS55150188A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5724979A JPS55150188A (en) 1979-05-10 1979-05-10 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5724979A JPS55150188A (en) 1979-05-10 1979-05-10 Memory circuit

Publications (2)

Publication Number Publication Date
JPS55150188A true JPS55150188A (en) 1980-11-21
JPS6236307B2 JPS6236307B2 (en) 1987-08-06

Family

ID=13050246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5724979A Granted JPS55150188A (en) 1979-05-10 1979-05-10 Memory circuit

Country Status (1)

Country Link
JP (1) JPS55150188A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5174535A (en) * 1974-12-25 1976-06-28 Hitachi Ltd
US4061954A (en) * 1975-12-29 1977-12-06 Mostek Corporation Dynamic random access memory system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5174535A (en) * 1974-12-25 1976-06-28 Hitachi Ltd
US4061954A (en) * 1975-12-29 1977-12-06 Mostek Corporation Dynamic random access memory system

Also Published As

Publication number Publication date
JPS6236307B2 (en) 1987-08-06

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