JPS5593587A - Sense amplifier circuit of mos memory - Google Patents

Sense amplifier circuit of mos memory

Info

Publication number
JPS5593587A
JPS5593587A JP16506278A JP16506278A JPS5593587A JP S5593587 A JPS5593587 A JP S5593587A JP 16506278 A JP16506278 A JP 16506278A JP 16506278 A JP16506278 A JP 16506278A JP S5593587 A JPS5593587 A JP S5593587A
Authority
JP
Japan
Prior art keywords
sense amplifier
sai
amplifier circuit
mosfet
interposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16506278A
Other languages
Japanese (ja)
Inventor
Keizo Aoyama
Hiroshi Shimada
Eiji Noguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16506278A priority Critical patent/JPS5593587A/en
Publication of JPS5593587A publication Critical patent/JPS5593587A/en
Pending legal-status Critical Current

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  • Static Random-Access Memory (AREA)

Abstract

PURPOSE: To make it possible to read data in a prescribed speed dependent upon a load provided on a data bus independently of a memory state, by providing a MOSFET, which has the column decoder controlled by the output, in the circuit of a sense amplifier.
CONSTITUTION: Enhancement MOSFET-T5i is interposed between transistor T1i and node Pi of sense amplifier SAi, and enhancement MOSFET-T6i is interposed between transistor T2i and node Pi of sense amplifier SAi, and they are controlled on and off by column decoder output Yi. As a result, decoder output Yi for non- selected Sai is L-level in case that sense amplifier Sa0 is selected, and T4i, T5i and T6i are turned off in SAi, and turning-on of T1i is prevented even if bit line BLi is H-levle and T1i can be turned on.
COPYRIGHT: (C)1980,JPO&Japio
JP16506278A 1978-12-29 1978-12-29 Sense amplifier circuit of mos memory Pending JPS5593587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16506278A JPS5593587A (en) 1978-12-29 1978-12-29 Sense amplifier circuit of mos memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16506278A JPS5593587A (en) 1978-12-29 1978-12-29 Sense amplifier circuit of mos memory

Publications (1)

Publication Number Publication Date
JPS5593587A true JPS5593587A (en) 1980-07-16

Family

ID=15805122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16506278A Pending JPS5593587A (en) 1978-12-29 1978-12-29 Sense amplifier circuit of mos memory

Country Status (1)

Country Link
JP (1) JPS5593587A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063786A (en) * 1983-09-17 1985-04-12 Fujitsu Ltd Sense amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5371539A (en) * 1976-12-08 1978-06-26 Hitachi Ltd Semiconductor memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5371539A (en) * 1976-12-08 1978-06-26 Hitachi Ltd Semiconductor memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6063786A (en) * 1983-09-17 1985-04-12 Fujitsu Ltd Sense amplifier
JPH0325875B2 (en) * 1983-09-17 1991-04-09 Fujitsu Ltd

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