JPS55149570A - Binary circuit in facsimile - Google Patents

Binary circuit in facsimile

Info

Publication number
JPS55149570A
JPS55149570A JP5833179A JP5833179A JPS55149570A JP S55149570 A JPS55149570 A JP S55149570A JP 5833179 A JP5833179 A JP 5833179A JP 5833179 A JP5833179 A JP 5833179A JP S55149570 A JPS55149570 A JP S55149570A
Authority
JP
Japan
Prior art keywords
signal
circuit
input
comparator
binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5833179A
Other languages
Japanese (ja)
Other versions
JPS6340073B2 (en
Inventor
Masao Tanaka
Makoto Yamamoto
Hiroshi Kuramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JUJO ENG CO Ltd
JUJO ENG KK
Original Assignee
JUJO ENG CO Ltd
JUJO ENG KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JUJO ENG CO Ltd, JUJO ENG KK filed Critical JUJO ENG CO Ltd
Priority to JP5833179A priority Critical patent/JPS55149570A/en
Publication of JPS55149570A publication Critical patent/JPS55149570A/en
Publication of JPS6340073B2 publication Critical patent/JPS6340073B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits
    • H04N1/403—Discrimination between the two tones in the picture signal of a two-tone original

Abstract

PURPOSE:To enable to judge the black and white automatically even the background and characters of original are in half-tone, by providing the slice level determining circuit with the binary circuit. CONSTITUTION:The read-in video signal is fed to the comparator 2 and the slice level determining circuit 3 from the automatic gain control unit 1, the slice level L2 output from the circuit 3 and the video signal L1 are compared at the comparator 2 and output as the binary signal L3 of black and white. The circuit 3 is composed of the resistors R1, R2 having resistance value of 1:k(0<k<1), operational amplifier 4, clamp circuit 6 consisting of the diode 5 for set value input, and integrator 7. Accordingly, when the video signal L1 shown in (a) is input to the circuit 3, it is clamped at the set value or less and is the signal L1' of amplification factor k as shown in (b), it is input to the integrator 7 to be the level signal L2 shown in (c), and input to the comparator 2, where the signal L2 and the signal L1 are compared to obtain the binary signal L3 shown in (d).
JP5833179A 1979-05-11 1979-05-11 Binary circuit in facsimile Granted JPS55149570A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5833179A JPS55149570A (en) 1979-05-11 1979-05-11 Binary circuit in facsimile

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5833179A JPS55149570A (en) 1979-05-11 1979-05-11 Binary circuit in facsimile

Publications (2)

Publication Number Publication Date
JPS55149570A true JPS55149570A (en) 1980-11-20
JPS6340073B2 JPS6340073B2 (en) 1988-08-09

Family

ID=13081313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5833179A Granted JPS55149570A (en) 1979-05-11 1979-05-11 Binary circuit in facsimile

Country Status (1)

Country Link
JP (1) JPS55149570A (en)

Also Published As

Publication number Publication date
JPS6340073B2 (en) 1988-08-09

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