JPS57148476A - Picture signal processing circuit - Google Patents

Picture signal processing circuit

Info

Publication number
JPS57148476A
JPS57148476A JP3442081A JP3442081A JPS57148476A JP S57148476 A JPS57148476 A JP S57148476A JP 3442081 A JP3442081 A JP 3442081A JP 3442081 A JP3442081 A JP 3442081A JP S57148476 A JPS57148476 A JP S57148476A
Authority
JP
Japan
Prior art keywords
level
signal
supplied
output
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3442081A
Other languages
Japanese (ja)
Other versions
JPH0253991B2 (en
Inventor
Yoshihiro Morioka
Hiroyuki Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3442081A priority Critical patent/JPS57148476A/en
Publication of JPS57148476A publication Critical patent/JPS57148476A/en
Publication of JPH0253991B2 publication Critical patent/JPH0253991B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)

Abstract

PURPOSE: To perform a nonlinear level compressing processing on picture signals with an excellent frequency characteristic, by performing signal processings by setting the clip level, knee point, and slope on the picture signals.
CONSTITUTION: An input picture signal is supplied from a terminal 1 to a clamping circuit 3 through a preamplifier 2, and the DC level of a black level is clamped. The output has two gains which are equal to each other, and is supplied to slicing circuits 4 and 5 whose each slice level can be set to a variable condition. These circuits 4 and 5 slice the signal into SL1 and SL2 (SL1<SL2), respectively, and supply each output to a signal mixing circuit 8. In the circuit 8, signals SL1 and SL2 are supplied across both terminals 9a and 9b of a variable resistor 9, and an output in which the waveform is mixed at a mixing ratio corresponding to the resistance ratio between a variable terminal 9c and the terminals 9a and 9b, is outputted from a terminal 11. When a clip level, a knee point PN and a slope are given from a resistor 6 at this moment, a white clip point PW can be obtained at a resistor 7.
COPYRIGHT: (C)1982,JPO&Japio
JP3442081A 1981-03-10 1981-03-10 Picture signal processing circuit Granted JPS57148476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3442081A JPS57148476A (en) 1981-03-10 1981-03-10 Picture signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3442081A JPS57148476A (en) 1981-03-10 1981-03-10 Picture signal processing circuit

Publications (2)

Publication Number Publication Date
JPS57148476A true JPS57148476A (en) 1982-09-13
JPH0253991B2 JPH0253991B2 (en) 1990-11-20

Family

ID=12413703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3442081A Granted JPS57148476A (en) 1981-03-10 1981-03-10 Picture signal processing circuit

Country Status (1)

Country Link
JP (1) JPS57148476A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130110A (en) * 1984-07-20 1986-02-12 Hitachi Ltd Signal processing circuit
JPS61195670U (en) * 1985-05-29 1986-12-05
JPS62157474A (en) * 1985-12-28 1987-07-13 Hitachi Ltd Video signal processing circuit
JPS6324763A (en) * 1986-07-17 1988-02-02 Matsushita Electric Ind Co Ltd High luminance compressing circuit in color camera
US5299000A (en) * 1992-06-17 1994-03-29 Zenith Electronics Corp. Video white signal compression and peaking

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5278309A (en) * 1975-12-24 1977-07-01 Sony Corp Tv receiver
JPS5542445U (en) * 1978-09-13 1980-03-19

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5542445B2 (en) * 1973-12-20 1980-10-30

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5278309A (en) * 1975-12-24 1977-07-01 Sony Corp Tv receiver
JPS5542445U (en) * 1978-09-13 1980-03-19

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130110A (en) * 1984-07-20 1986-02-12 Hitachi Ltd Signal processing circuit
JPS61195670U (en) * 1985-05-29 1986-12-05
JPS62157474A (en) * 1985-12-28 1987-07-13 Hitachi Ltd Video signal processing circuit
JPS6324763A (en) * 1986-07-17 1988-02-02 Matsushita Electric Ind Co Ltd High luminance compressing circuit in color camera
US5299000A (en) * 1992-06-17 1994-03-29 Zenith Electronics Corp. Video white signal compression and peaking

Also Published As

Publication number Publication date
JPH0253991B2 (en) 1990-11-20

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