JPS61195670U - - Google Patents

Info

Publication number
JPS61195670U
JPS61195670U JP7923285U JP7923285U JPS61195670U JP S61195670 U JPS61195670 U JP S61195670U JP 7923285 U JP7923285 U JP 7923285U JP 7923285 U JP7923285 U JP 7923285U JP S61195670 U JPS61195670 U JP S61195670U
Authority
JP
Japan
Prior art keywords
video signal
input video
processing circuit
controlling
signal processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7923285U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7923285U priority Critical patent/JPS61195670U/ja
Publication of JPS61195670U publication Critical patent/JPS61195670U/ja
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第２図は従来の非線形処理回路の入出力特性図
、第１図は本考案の非線形処理回路の一例を示す
ブロツク図、第３図はこの非線形処理回路の入出
力特性を説明するための図である。 ４，５，６：利得制御回路、７，８，９：クラ
ンプ回路、１０，１１，１２：黒非加算混合回路
、１３：ピークホールド回路、１４：加算回路、
１５：積分回路。 Fig. 2 is an input/output characteristic diagram of a conventional nonlinear processing circuit, Fig. 1 is a block diagram showing an example of the nonlinear processing circuit of the present invention, and Fig. 3 is a diagram for explaining the input/output characteristics of this nonlinear processing circuit. It is. 4, 5, 6: gain control circuit, 7, 8, 9: clamp circuit, 10, 11, 12: black non-addition mixing circuit, 13: peak hold circuit, 14: addition circuit,
15: Integrating circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力映像信号を非線形処理する映像信号処理回
路において、入力映像信号の最大値を検出する手
段と、該入力映像信号の平均値を検出する手段と
、上記映像信号処理回路にニー点とスロープを制
御する手段をもち、上記検出した入力映像信号の
最大値に基づきスロープを、上記検出した入力映
像信号の平均値に基づきニー点を制御する構成し
としたことを特徴とする映像信号処理回路。 A video signal processing circuit that non-linearly processes an input video signal, comprising means for detecting a maximum value of the input video signal, means for detecting an average value of the input video signal, and controlling a knee point and slope for the video signal processing circuit. 1. A video signal processing circuit, comprising means for controlling a slope based on the maximum value of the detected input video signal and controlling a knee point based on the average value of the detected input video signal.
JP7923285U 1985-05-29 1985-05-29 Pending JPS61195670U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7923285U JPS61195670U (en) 1985-05-29 1985-05-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7923285U JPS61195670U (en) 1985-05-29 1985-05-29

Publications (1)

Publication Number Publication Date
JPS61195670U true JPS61195670U (en) 1986-12-05

Family

ID=30623952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7923285U Pending JPS61195670U (en) 1985-05-29 1985-05-29

Country Status (1)

Country Link
JP (1) JPS61195670U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423569A (en) * 1990-05-18 1992-01-27 Sony Corp Video signal compression circuit
WO2001039495A1 (en) * 1999-11-25 2001-05-31 Matsushita Electric Industrial Co., Ltd. Method and apparatus for gradation correction, and video display

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4721050U (en) * 1971-03-01 1972-11-09
JPS53129523A (en) * 1977-04-18 1978-11-11 Hitachi Denshi Ltd White clip circuit
JPS5437522A (en) * 1977-08-30 1979-03-20 Hitachi Denshi Ltd Camma correction circuit
JPS57148476A (en) * 1981-03-10 1982-09-13 Sony Corp Picture signal processing circuit
JPS604082B2 (en) * 1974-11-20 1985-02-01 スピードラツク・インコーポレーテツド storage shelf
JPS6011561B2 (en) * 1979-04-04 1985-03-27 新日本製鐵株式会社 Slab width reduction rolling method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4721050U (en) * 1971-03-01 1972-11-09
JPS604082B2 (en) * 1974-11-20 1985-02-01 スピードラツク・インコーポレーテツド storage shelf
JPS53129523A (en) * 1977-04-18 1978-11-11 Hitachi Denshi Ltd White clip circuit
JPS5437522A (en) * 1977-08-30 1979-03-20 Hitachi Denshi Ltd Camma correction circuit
JPS6011561B2 (en) * 1979-04-04 1985-03-27 新日本製鐵株式会社 Slab width reduction rolling method
JPS57148476A (en) * 1981-03-10 1982-09-13 Sony Corp Picture signal processing circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423569A (en) * 1990-05-18 1992-01-27 Sony Corp Video signal compression circuit
WO2001039495A1 (en) * 1999-11-25 2001-05-31 Matsushita Electric Industrial Co., Ltd. Method and apparatus for gradation correction, and video display

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