JPS55133159A - Timing extraction circuit - Google Patents
Timing extraction circuitInfo
- Publication number
- JPS55133159A JPS55133159A JP3977579A JP3977579A JPS55133159A JP S55133159 A JPS55133159 A JP S55133159A JP 3977579 A JP3977579 A JP 3977579A JP 3977579 A JP3977579 A JP 3977579A JP S55133159 A JPS55133159 A JP S55133159A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- rate
- timing extraction
- peaks
- smaller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To enable timing extraction even with a jitter distribution having two peaks, by increasing or decreasing in stepwise a change in an oscillation frequency in response to a phase difference output is greater or smaller than N0 clock. CONSTITUTION:The phase comparator 2 counts the phase difference between the input signal d and the output e of the variable frequency oscillator 22 and outputs it as the signal f. The signal f is fed to the control signal generating circuit 28 consisting of the up-down counters 24, 25 being the first and second integration circuits and the quantizing cirucuit 23. Taking the clock number of a half of the interval of the two peaks as N0, and the pulse for the signals m and n as Nm and Nn, when the count number N of the signal f, is smaller than -N0 or greater than N0, the rate of the Nm, Nn produced to the count number N is 8 times the rate between -N0 and N0, and when the rate of change of the oscillation frequency is greater than N0, it is 8.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54039775A JPS6017263B2 (en) | 1979-04-04 | 1979-04-04 | timing extraction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54039775A JPS6017263B2 (en) | 1979-04-04 | 1979-04-04 | timing extraction circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55133159A true JPS55133159A (en) | 1980-10-16 |
JPS6017263B2 JPS6017263B2 (en) | 1985-05-01 |
Family
ID=12562300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54039775A Expired JPS6017263B2 (en) | 1979-04-04 | 1979-04-04 | timing extraction circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6017263B2 (en) |
-
1979
- 1979-04-04 JP JP54039775A patent/JPS6017263B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6017263B2 (en) | 1985-05-01 |
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