JPS55133159A - Timing extraction circuit - Google Patents

Timing extraction circuit

Info

Publication number
JPS55133159A
JPS55133159A JP3977579A JP3977579A JPS55133159A JP S55133159 A JPS55133159 A JP S55133159A JP 3977579 A JP3977579 A JP 3977579A JP 3977579 A JP3977579 A JP 3977579A JP S55133159 A JPS55133159 A JP S55133159A
Authority
JP
Japan
Prior art keywords
signal
rate
timing extraction
peaks
smaller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3977579A
Other languages
Japanese (ja)
Other versions
JPS6017263B2 (en
Inventor
Toru Koyama
Toshihiko Wakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP54039775A priority Critical patent/JPS6017263B2/en
Publication of JPS55133159A publication Critical patent/JPS55133159A/en
Publication of JPS6017263B2 publication Critical patent/JPS6017263B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To enable timing extraction even with a jitter distribution having two peaks, by increasing or decreasing in stepwise a change in an oscillation frequency in response to a phase difference output is greater or smaller than N0 clock. CONSTITUTION:The phase comparator 2 counts the phase difference between the input signal d and the output e of the variable frequency oscillator 22 and outputs it as the signal f. The signal f is fed to the control signal generating circuit 28 consisting of the up-down counters 24, 25 being the first and second integration circuits and the quantizing cirucuit 23. Taking the clock number of a half of the interval of the two peaks as N0, and the pulse for the signals m and n as Nm and Nn, when the count number N of the signal f, is smaller than -N0 or greater than N0, the rate of the Nm, Nn produced to the count number N is 8 times the rate between -N0 and N0, and when the rate of change of the oscillation frequency is greater than N0, it is 8.
JP54039775A 1979-04-04 1979-04-04 timing extraction circuit Expired JPS6017263B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54039775A JPS6017263B2 (en) 1979-04-04 1979-04-04 timing extraction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54039775A JPS6017263B2 (en) 1979-04-04 1979-04-04 timing extraction circuit

Publications (2)

Publication Number Publication Date
JPS55133159A true JPS55133159A (en) 1980-10-16
JPS6017263B2 JPS6017263B2 (en) 1985-05-01

Family

ID=12562300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54039775A Expired JPS6017263B2 (en) 1979-04-04 1979-04-04 timing extraction circuit

Country Status (1)

Country Link
JP (1) JPS6017263B2 (en)

Also Published As

Publication number Publication date
JPS6017263B2 (en) 1985-05-01

Similar Documents

Publication Publication Date Title
DE3071902D1 (en) Device for phase synchronization
GB940840A (en) Apparatus for controlling the frequency of an oscillation generator
JPS6413814A (en) Phase locking loop locking synchronizer and signal detector
JPS5485661A (en) Clock pulse reproducing circuit
JPS6419827A (en) Synchronizing device
JPS5458467A (en) Electronic watch
JPS55133159A (en) Timing extraction circuit
EP0026639A3 (en) Clock recovery network
JPS5679524A (en) Conversion circuit for duty cycle
JPS564938A (en) Phase synchronizing circuit
JPS5381059A (en) Digital phase synchronizing system
JPS55135448A (en) Extracting system for manchester code clock
JPS5579526A (en) Digital type delay circuit
JPS5720169A (en) Digital pulse phase shifter
JPS55128188A (en) Electronic watch
JPS54150065A (en) Fm signal demodulator
JPS55115737A (en) Digital phase synchronism circuit
JPS55166478A (en) Pulse phase shift circuit
JPS54146944A (en) Digital pulse phase shifter
JPS5286758A (en) High accurate digital delay circuit
JPS5687939A (en) Phase synchronizing circuit
JPS53133354A (en) Phase synchronizing circuit
GB1105562A (en) Synchronous clock pulse generator
JPS5479015A (en) Sampling pulse generating circuit
JPS5696526A (en) Timing signal generating system