GB1105562A - Synchronous clock pulse generator - Google Patents
Synchronous clock pulse generatorInfo
- Publication number
- GB1105562A GB1105562A GB913565A GB913565A GB1105562A GB 1105562 A GB1105562 A GB 1105562A GB 913565 A GB913565 A GB 913565A GB 913565 A GB913565 A GB 913565A GB 1105562 A GB1105562 A GB 1105562A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulse
- data
- counter
- component
- pulses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000001360 synchronised effect Effects 0.000 title abstract 2
- 230000002441 reversible effect Effects 0.000 abstract 2
- 238000006243 chemical reaction Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
1,105,562. Synchronizing clock pulses with data. TELEMETRICS Inc. 3 March, 1965, No. 9135/65. Heading G4C. [Also in Division H3] A synchronous clock pulse generator system for responding to intermittent bursts of digital data pulses of variable repetition rate, comprises an oscillator to generate clock pulses and means to compare their phase with that of the data pulses, the oscillator being controlled by a bias voltage controlled by a reversible counter to reduce any phase difference. Digital data signals 11, from magnetic tape or a radio receiver and which may use a signal level change for bit 1 and no change for 0, are converted to pulse/no pulse form at 20. The data signals are gated with. clock pulses from a generator 70 driven by an oscillator 60 via frequencydivider counter 50, the latter producing an output at a predetermined count preselected by a switching circuit 55. The data pulses, in the pulse/no pulse form, are applied via a delay 25 to a reversible counter 40 which counts each pulse (each 1) up or down depending on the relative time of occurrence of the data pulse and the current clock pulse (i.e. which occurs first), as determined by up/down circuit 30. The count in upper stages of the counter 40 is converted to analogue form at 80 and used as one component of a bias voltage which controls the frequency of oscillator 60 so as to synchronize the data and clock pulses. The lower stages of the counter 40 pass a pulse, to the upper stages on reaching a predetermined count preselected by a switching circuit. The effects of noise are reduced by not using all stages of the counter 40 for the digital-toanalogue conversion 80. Each pulse from the up/down circuit 30 also produces directly a momentary positive or negative second component to the bias voltage. This second component is three or four times the size of the minimum change which can occur in the first component. The use of the second component eliminates instability in the loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB913565A GB1105562A (en) | 1965-03-05 | 1965-03-05 | Synchronous clock pulse generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB913565A GB1105562A (en) | 1965-03-05 | 1965-03-05 | Synchronous clock pulse generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1105562A true GB1105562A (en) | 1968-03-06 |
Family
ID=9866048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB913565A Expired GB1105562A (en) | 1965-03-05 | 1965-03-05 | Synchronous clock pulse generator |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1105562A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114400889A (en) * | 2022-01-25 | 2022-04-26 | 上海感与执技术有限公司 | Output voltage control circuit and method for charge pump |
-
1965
- 1965-03-05 GB GB913565A patent/GB1105562A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114400889A (en) * | 2022-01-25 | 2022-04-26 | 上海感与执技术有限公司 | Output voltage control circuit and method for charge pump |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1448712A (en) | Digital speed control | |
| GB1497301A (en) | Phase comparison systems employing phaselock loop apparatus | |
| GB885139A (en) | Digital synchronization circuit | |
| GB1440390A (en) | Signal generating circuit | |
| GB1294759A (en) | Variable frequency oscillator control systems | |
| GB1353791A (en) | Digital signal synchronizing system | |
| GB1491899A (en) | Signal generator arrangement | |
| ES473448A1 (en) | Digital frequency divider | |
| US3370252A (en) | Digital automatic frequency control system | |
| GB1429621A (en) | Display systems | |
| GB1447418A (en) | Frequency synthesiser | |
| GB1406898A (en) | Frequency comparator system | |
| CA1216032A (en) | Variable digital frequency generator with value storage | |
| GB1111355A (en) | Stabilised variable oscillator | |
| GB1105562A (en) | Synchronous clock pulse generator | |
| GB1355028A (en) | Synchronising systems for phase-difference-modulated data signals | |
| GB1049916A (en) | Method for synchronizing electrical circuits | |
| GB1264869A (en) | ||
| GB1149684A (en) | Servo system | |
| GB1333534A (en) | Variable-freqeuncy generator | |
| JPS5535545A (en) | Digital phase synchronous circuit | |
| GB1447504A (en) | Radar receivers | |
| GB1242457A (en) | A method and circuit for the control of oscillators | |
| GB1393266A (en) | Data transmission synchronising circuits | |
| GB1169460A (en) | Electronic Apparatus Forming a Frequency Memory. |