GB1393266A - Data transmission synchronising circuits - Google Patents

Abstract

1393266 Data transmission; synchronizing SIEMENS AG 11 Dec 1972 [21 Dec 1971] 57065/72 Heading H4C Locally generated pulses at a data receiver are pulled into phase with received pulses by an error signal which is derived from the net count of a reversible counter controlled by the two sets of pulses. A pulse generator 25 in the local receiver Fig. 2, drives a divider 26 producing three outputs A, E, F, Fig. 3, where F is twice the frequency of A. The received signal B1 at 27 goes to a circuit 28 which produces pulses C4, C5 corresponding to positive and negative edges respectively of B1. These set respective bi-stables 31, 32, which are reset by the next following F pulses (F2, F4) from the divider 26, thus generating pulses K1, K2 whose duration is related to the phase difference between the received pulses B1 and the local pulses F. These pulses K1, K2 enable a gate 12 to pass the generator 25 output pulses to the counter 22, which counts up while E is 1 and down while E is 0. The polarity of the final count at t 11 thus depends on the phase difference between E and the K1, K2 pulses and hence between E and the received pulses B1. The concidence of F4 and K21 at time t 11 opens a gate 18 and enables gates 15, 16 to pass to respective inputs a, c of the divider 26 the output f of the counter 22, which is 1 for a positive net count and 0 for negative net count. The divider 26 is consequently increased or decreased in dividing ratio to reduce the phase error. A bi-stable 29 regenerates the received signal B1 in response to the now locked local signal A. Counter 22 is reset by the gate 18 output at t 11 through a delay circuit 24. In a modification (Fig. 5, not shown), a further bi-stable (33) and a second counter (23) are added, the counter (23) producing outputs (h and k) to change the divider 26 ratio only if the count exceeds upper or lower limits + N, - N. In another modification (Fig. 8, not shown), a single counter is used (30) which produces separate outputs (f, g) for opposite counts, and further outputs (h, e) when upper and lower limits ŒS are exceeded; and also has a fourth bi-stable (34). In this case the speed at which the circuit corrects any phase error between the received and local signals is proportional to the actual size of the error.