GB1333534A - Variable-freqeuncy generator - Google Patents

Abstract

1333534 Frequency generators THOMSONCSF 1 March 1972 [2 March 1971] 9645/72 Heading H3A A frequency generator for generating frequencies of the form NFr, where N is a variable integer and Fr a stable reference frequency, comprises a stable device for delivering the frequency Fr and a second stable frequency k.Fr, where k is an integer greater than 1, a variable-frequency oscillator of output frequency F, a main circuit comprising dividing means for deriving from the oscillator output a signal of frequency F/N and also comprising means for locking the frequency F/N to the frequency Fr, an auxiliary circuit, comprising dividing means for deriving from the output signal F a signal of frequency F/q, q being equal to N/k + e, where e is zero or small as compared with N/k, and also comprising further means for delivering an error signal proportional to the algebraical difference between the duration of the periods respectively corresponding to the frequencies F/q and k.Fr, and control means for, for each frequency N.Fr to be generated, causing the auxiliary and main circuits to operate successively. In an embodiment, the desired frequency F appears at output 20, Fig. 1, of variable frequency oscillator 1, the frequency of which is controlled by control circuit 6. A stabilized reference frequency oscillator 7 is also provided. The output from oscillator 1 is also fed to decimally-controlled divider 3, while oscillator 7 feeds reference divider 8 which comprises two seriesconnected counters whose outputs are alternately connected by a switch to a bi-stable circuit providing the reference divider output; the first counter produces one output pulse for Z/2 pulses from oscillator 7, while the second counter produces one output pulse for k pulses from the first counter. A comparator 5 provides an output 55 to control circuit 6 and has a first input derived from divider 3 over monostable trigger 4, and two further inputs 51, 52 respectively derived from divider 8 directly and via a monostable trigger 9. The division ratio of divider 3 is set up by selecting device 13 either via electronic switch 11 or switch 12, via OR gates (shown as dots): device 13 operates under control of remote control receiver 14, outputs 41 of which define the frequency to be set up while output 40 provides a synchronizing output which is applied to two-output bi-stable trigger 15, to OR gate 2 and to a reset input of a counter 18. OR gate 2 provides an output resetting dividers 3, 23. The output from monostable trigger 4 also energizes a further monostable trigger 16, the output from which is fed to counter 18 and OR gate 2. Selecting device 13 produces a third output which is converted to analogue form in digital-to-analogue converter 10. The control circuit 6 comprises an addition circuit with storage properties which produces the sum of the output signal from converter 10 and the signal resulting from integration of successive output signals from comparator 5; it is constituted by two AND gates 53, 54, Fig. 2, inverter 56 and resistor 57, terminal 60 being coupled by capacitor 62, 65 to the base of emitter-follower 63 which provides the output at terminal 61. Operation.-Upon selection of a new frequency a sync. pulse, on terminal 40, occurring at time t 0 (Fig. 3) resets counter 18 and also, via OR gate 2, dividers 3, 8; it also trips trigger circuit 15 whereby AND gate 17 is blocked, switch 12 opened and switch 11 closed, so that divider 3 is given the division ratio g=N/K. It causes the production of the frequency kFr at the output of reference divider 8. Selecting device 13 supplies an input to converter 10 which applies a control signal to oscillator 1 whereby it produces a frequency (Fe+#F) approximately equal to the desired frequency Fe. Let α be the absolute maximum value of #F/Fe and let L=α#, where L is the duration of the quasistable state of each of the monostable circuits 4, 9, 16. The variable divider 3 produces at time t<SP>1</SP> a short pulse which is converted into a pulse I 1 of length L by trigger circuit 4; the time t<SP>1</SP>-t 0 = 1/(Fe+#F). The pulse I 1 is applied to the monostable trigger 16 which, having an output differentiator, supplies a short pulse at time L following the trailing edge of I 1 , i.e. at time t<SP>1</SP> + 2L=t 1 ; this pulse is supplied through gate 17 to OR gate 2 to reset dividers 3, 8, and also to counter 18. At output 51 there appears between time t 0 and t 1 a signal R 1 , whereas, due to monostable trigger 9, there appears at input 52 a signal R 1 <SP>1</SP>: pairs of simultaneous signals obtained in the same fashion as R 1 and R 1 <SP>1</SP> are applied to the respective inputs of comparator 5 until counter 18 has been supplied at input 28 with the number of pulses corresponding to the desired number m of pairs of simultaneous signals; whereupon counter 18 supplies a signal which trips trigger circuit 15 into its other state. If m= 1 counter 18 reduces to a single trigger circuit which trips trigger circuit 15 at instant t 1 . When trigger circuit 15 is tripped, gate 17 is blocked, inhibiting feeding of counter 18, and also supply of reset signals to dividers 3, 8; switch 11 is blocked and switch 12 unblocked, changing the ratio of divider 3 to N, and tripping the switch in divider 8, so as to produce the frequency Fr at its output. Consequently after instant t 1 , the variable divider 3 supplies short pulses of frequency F/N which are converted by trigger circuit 4 to pulses I 2 of length L; reference divider 8 supplies a rectangular waveform R 2 of frequency Fr and periodicity Tr, while trigger circuit 9 supplies a signal R 2 <SP>1</SP>. If then #F = O, t<SP>1</SP> = (t 0 + #) and the comparator 5 will produce no output; if #F is positive t<SP>1</SP><(t 0 + #) and the comparator produces a positive control output, whereas if #F is negative t<SP>1</SP>>(t 0 +#) and a negative control signal is produced.