JPS5579526A - Digital type delay circuit - Google Patents

Digital type delay circuit

Info

Publication number
JPS5579526A
JPS5579526A JP15310778A JP15310778A JPS5579526A JP S5579526 A JPS5579526 A JP S5579526A JP 15310778 A JP15310778 A JP 15310778A JP 15310778 A JP15310778 A JP 15310778A JP S5579526 A JPS5579526 A JP S5579526A
Authority
JP
Japan
Prior art keywords
counter
circuit
output
signal
delay time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15310778A
Other languages
Japanese (ja)
Inventor
Hiroo Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15310778A priority Critical patent/JPS5579526A/en
Publication of JPS5579526A publication Critical patent/JPS5579526A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to vary delay time freely, by providing a control oscillator which provides external variation in oscillation frequency, a counter for a decrease in oscillation frequency, and a switch circuit which controls this counter.
CONSTITUTION: Applying input signal (i1) to set-reset type FF6 sets FF6, and then pulses of a frequency set by voltage setter 1, generated by voltage control oscillator 2, appear at the output of AND circuit 3. On receiving a signal from output Q' of FF6, differentiating circuit 7 outputs differential outputs of a high level to set n- scale counter 4, thereby starting to count output pulses of circuit 3. When the counter is reset by counting an n-th pulse, differentiating circuit 5 is held at a high level to output signal O1 with delay time T from signal (i1). Simultaneously, FF6 is reset, stopping counter 4. Therefore, varying the set value of setter 1 varies a frequency freely, so that any delay time can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP15310778A 1978-12-13 1978-12-13 Digital type delay circuit Pending JPS5579526A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15310778A JPS5579526A (en) 1978-12-13 1978-12-13 Digital type delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15310778A JPS5579526A (en) 1978-12-13 1978-12-13 Digital type delay circuit

Publications (1)

Publication Number Publication Date
JPS5579526A true JPS5579526A (en) 1980-06-16

Family

ID=15555116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15310778A Pending JPS5579526A (en) 1978-12-13 1978-12-13 Digital type delay circuit

Country Status (1)

Country Link
JP (1) JPS5579526A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374830U (en) * 1986-10-31 1988-05-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6374830U (en) * 1986-10-31 1988-05-18

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