JPS55125647A - Semiconductor device and production of the same - Google Patents
Semiconductor device and production of the sameInfo
- Publication number
- JPS55125647A JPS55125647A JP3311979A JP3311979A JPS55125647A JP S55125647 A JPS55125647 A JP S55125647A JP 3311979 A JP3311979 A JP 3311979A JP 3311979 A JP3311979 A JP 3311979A JP S55125647 A JPS55125647 A JP S55125647A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring structure
- aluminum
- acid
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To obtain a multi-layered wiring structure with a desired taper by preparing a wiring structure consisting of a lower layer of pure aluminum and an upper layer of Cu-added aluminum, and subjecting the wiring structure to chemical etching. CONSTITUTION:A pure-aluminum layer 12 is formed by sputtering on a PSG film 11 formed on a Si substrate 10. An aluminum layer 13 containing approximately 4 wt.% of Cu is formed in the same manner on the layer 12. A resist mask 14 is formed on the layer 13, and the aluminum is etched with a mixture of sulfuric acid, acetic acid and nitric acid. As a result, the layer 13 is etched early so that the aluminum layers are changed into a trapezoidal form having an angle theta of 60-70 deg.. In the resulting wiring structure having such an angle as mentioned above, breaking of wire never occurs. When an etching solution consisting of the above-mentioned mixture and water, in which the composition ratio of sulfuric acid, acetic acid, nitric acid and water is 16:1:1:2, is used, a wiring structure having a smooth and ideally curved bottom surface can be obtained. According to this method, aluminum wiring with a desired taper can be obtained by simple etching, and this method can be advantageously used to form a multi-layer wiring structure. Moreover, this wiring structure has a high electromigration resistance, and permits maintaining a high current density.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3311979A JPS55125647A (en) | 1979-03-20 | 1979-03-20 | Semiconductor device and production of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3311979A JPS55125647A (en) | 1979-03-20 | 1979-03-20 | Semiconductor device and production of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55125647A true JPS55125647A (en) | 1980-09-27 |
Family
ID=12377735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3311979A Pending JPS55125647A (en) | 1979-03-20 | 1979-03-20 | Semiconductor device and production of the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55125647A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5336363A (en) * | 1993-09-24 | 1994-08-09 | Applied Materials, Inc. | Low temperature dry etch of copper |
-
1979
- 1979-03-20 JP JP3311979A patent/JPS55125647A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5336363A (en) * | 1993-09-24 | 1994-08-09 | Applied Materials, Inc. | Low temperature dry etch of copper |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3586922A (en) | Multiple-layer metal structure and processing | |
JPS55125647A (en) | Semiconductor device and production of the same | |
KR900002315A (en) | Isolation Transmission Line and Forming Method | |
JPS55102235A (en) | Formation of interlayer conductive layer | |
JPS56155550A (en) | Multilayer wiring structure and manufacture thereof | |
JPS57145327A (en) | Manufacture of semiconductor device | |
JPS6476797A (en) | Manufacture of superconducting thin-film multi-layer board | |
JPS5513995A (en) | Method of producing a semiconductor device | |
JPS5469393A (en) | Production of semiconductor device | |
JPS6466953A (en) | Semiconductor device | |
JPS5654051A (en) | Formation of electrode wiring | |
JPS5687326A (en) | Method of forming wiring | |
JPS6451698A (en) | Manufacture of superconducting thin film multilayer board | |
JPS5526686A (en) | Manufacturing semiconductor device | |
JPS56114355A (en) | Manufacture of semiconductor device | |
JPS5546587A (en) | Method of forming plasma growing film | |
JPS57169259A (en) | Manufacture of semiconductor device | |
JPS5538061A (en) | Bridging wiring method | |
JPS55153352A (en) | Forming method of aluminum conductive layer | |
JPS6444045A (en) | Wiring structure of semiconductor device | |
JPS5527644A (en) | Multi-layer wiring type semiconductor device | |
JPS54113277A (en) | Production of semiconductor device | |
JPS56164569A (en) | Semiconductor device | |
JPS5768035A (en) | Manufacture of semiconductor device | |
JPS55118652A (en) | Manufacture of semiconductor device |