JPS55124845A - Digital multiplier - Google Patents

Digital multiplier

Info

Publication number
JPS55124845A
JPS55124845A JP3367279A JP3367279A JPS55124845A JP S55124845 A JPS55124845 A JP S55124845A JP 3367279 A JP3367279 A JP 3367279A JP 3367279 A JP3367279 A JP 3367279A JP S55124845 A JPS55124845 A JP S55124845A
Authority
JP
Japan
Prior art keywords
circuit
multiplier
product
output
multiplicand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3367279A
Other languages
Japanese (ja)
Inventor
Atsushi Yamada
Yoshifumi Amamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP3367279A priority Critical patent/JPS55124845A/en
Publication of JPS55124845A publication Critical patent/JPS55124845A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the capacity of ROM in the digital multiplier using read-only memory (ROM) as the circuit in which the result of square is picked up at the output to the address value written in advance.
CONSTITUTION: The product AB is obtained from equation (1), by taking A as multiplier and B as multiplicand. The multiplier A and multiplicand B are inputted respectively from the input terminals 8 and 9, and A+B is obtained at the addition circuit 1 and A-B is obtained at subtraction circuit 2. Division is made by 2, the least significant bit LSD is omitted, the output is inputted to the square tables 3, 4 consisting of ROM through address to obtain the square value as the output. Subtraction is made at the next subtraction circuit and the product AB is obtained at the product output terminal 10. When the numbers A, B are both an even or odd number, correct value can be obtained. But if different, error can be produced. Discrimination is made at the selection circuit 6 to discriminate the greatness of multiplier and multiplicand, smaller number is fed to the addition circuit 7, it is added with the result of the subtraction circuit 5 for correct product.
COPYRIGHT: (C)1980,JPO&Japio
JP3367279A 1979-03-22 1979-03-22 Digital multiplier Pending JPS55124845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3367279A JPS55124845A (en) 1979-03-22 1979-03-22 Digital multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3367279A JPS55124845A (en) 1979-03-22 1979-03-22 Digital multiplier

Publications (1)

Publication Number Publication Date
JPS55124845A true JPS55124845A (en) 1980-09-26

Family

ID=12392937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3367279A Pending JPS55124845A (en) 1979-03-22 1979-03-22 Digital multiplier

Country Status (1)

Country Link
JP (1) JPS55124845A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752731A (en) * 1985-06-14 1988-06-21 Mitsubishi Denki Kabushiki Kaisha Electronic type electric energy meter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4752731A (en) * 1985-06-14 1988-06-21 Mitsubishi Denki Kabushiki Kaisha Electronic type electric energy meter

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