JPS55124255A - Self-substrate bias circuit - Google Patents
Self-substrate bias circuitInfo
- Publication number
- JPS55124255A JPS55124255A JP3189979A JP3189979A JPS55124255A JP S55124255 A JPS55124255 A JP S55124255A JP 3189979 A JP3189979 A JP 3189979A JP 3189979 A JP3189979 A JP 3189979A JP S55124255 A JPS55124255 A JP S55124255A
- Authority
- JP
- Japan
- Prior art keywords
- capacity
- self
- substrate bias
- substrate
- coupling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title abstract 7
- 230000008878 coupling Effects 0.000 abstract 4
- 238000010168 coupling process Methods 0.000 abstract 4
- 238000005859 coupling reaction Methods 0.000 abstract 4
- 230000003071 parasitic effect Effects 0.000 abstract 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
- H01L27/0222—Charge pumping, substrate bias generation structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To regulate the threshold value of a MOS circuit by forming a pair of conductive layers in space in an insulating layer on a semiconductor circuit substrate, forming a capacity passing Al component of an input signal, and rectifying the AC component to provide a DC self-substrate bias. CONSTITUTION:An insulating oxide layer 21 is formed on the surface of a p-type circuit substrate 5, a pair of conductive layers 22, 23 such as polysilicon or the like are formed in space in the layer 21, and electrodes 24, 25 such as aluminum or the like are connected to the respective layers. A coupling capacity 2' is formed between the electrodes 24 and 25, and a parasitic capacity 8' is formed between the electrode 25 and the substrate 5. Since the capacitance of the capacity 8' is approx. 18% of the coupling capacity 2', the total capacity of the coupling capacity can be sufficiently increased with respect to the total capacity of the parasitic capacity. Thus, the AC component passed through the coupling capacity is rectified to be used as a self-substrate bias. Since the parasitic capacity hardly affects it, the time constant become short. Therefore, even if the pulse signal is high frequency, desired self-substrate bias voltage can be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3189979A JPS55124255A (en) | 1979-03-19 | 1979-03-19 | Self-substrate bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3189979A JPS55124255A (en) | 1979-03-19 | 1979-03-19 | Self-substrate bias circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55124255A true JPS55124255A (en) | 1980-09-25 |
Family
ID=12343850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3189979A Pending JPS55124255A (en) | 1979-03-19 | 1979-03-19 | Self-substrate bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55124255A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4914546A (en) * | 1989-02-03 | 1990-04-03 | Micrel Incorporated | Stacked multi-polysilicon layer capacitor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3806741A (en) * | 1972-05-17 | 1974-04-23 | Standard Microsyst Smc | Self-biasing technique for mos substrate voltage |
-
1979
- 1979-03-19 JP JP3189979A patent/JPS55124255A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3806741A (en) * | 1972-05-17 | 1974-04-23 | Standard Microsyst Smc | Self-biasing technique for mos substrate voltage |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4914546A (en) * | 1989-02-03 | 1990-04-03 | Micrel Incorporated | Stacked multi-polysilicon layer capacitor |
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