JPS55121543A - Area decision circuit - Google Patents

Area decision circuit

Info

Publication number
JPS55121543A
JPS55121543A JP2843279A JP2843279A JPS55121543A JP S55121543 A JPS55121543 A JP S55121543A JP 2843279 A JP2843279 A JP 2843279A JP 2843279 A JP2843279 A JP 2843279A JP S55121543 A JPS55121543 A JP S55121543A
Authority
JP
Japan
Prior art keywords
circuit
address
via line
data
decision circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2843279A
Other languages
Japanese (ja)
Inventor
Hirofumi Kasugai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2843279A priority Critical patent/JPS55121543A/en
Publication of JPS55121543A publication Critical patent/JPS55121543A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To simplify the constitution by reducing its hardware by providing a circuit which is stored with a decision signal, showing whether an arithmetic result is included in a predetermined area, at an address assigned by the arithmetic result.
CONSTITUTION: Data X supplied via line 51 and data Y via line 52 are subtracted by arithmetic circuit 5. Output data X-Y of circuit 5 is sent as an 8-bit address to read-only memory circuit 6 via line 53. Circuit 6 is stored with the result of a comparison between |X-Y| and data T. At an address of |X-Y|<T, logic "1" is written and at an address of |X-Y|≥T, logic "0" is also set. The address sent via line 53 is a decimal number satisfying -128≤X-Y≤+127 because of eight bits.
COPYRIGHT: (C)1980,JPO&Japio
JP2843279A 1979-03-12 1979-03-12 Area decision circuit Pending JPS55121543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2843279A JPS55121543A (en) 1979-03-12 1979-03-12 Area decision circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2843279A JPS55121543A (en) 1979-03-12 1979-03-12 Area decision circuit

Publications (1)

Publication Number Publication Date
JPS55121543A true JPS55121543A (en) 1980-09-18

Family

ID=12248492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2843279A Pending JPS55121543A (en) 1979-03-12 1979-03-12 Area decision circuit

Country Status (1)

Country Link
JP (1) JPS55121543A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065332A (en) * 1983-09-19 1985-04-15 Ando Electric Co Ltd Signal deciding circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6065332A (en) * 1983-09-19 1985-04-15 Ando Electric Co Ltd Signal deciding circuit

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