JPS55915A - Display unit - Google Patents

Display unit

Info

Publication number
JPS55915A
JPS55915A JP7284778A JP7284778A JPS55915A JP S55915 A JPS55915 A JP S55915A JP 7284778 A JP7284778 A JP 7284778A JP 7284778 A JP7284778 A JP 7284778A JP S55915 A JPS55915 A JP S55915A
Authority
JP
Japan
Prior art keywords
register
bit
buffers
character code
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7284778A
Other languages
Japanese (ja)
Inventor
Tadashi Kyoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7284778A priority Critical patent/JPS55915A/en
Publication of JPS55915A publication Critical patent/JPS55915A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To obtain a display unit capable of displaying more characters by using memory buffers with the same capacity.
CONSTITUTION: When bit (n) set to register 3 is "1", register 3 makes memory address counter 1 count up by one, a character code is read out from the next address (A+1), and the character code part is set, n/2 bit by n/2 bit, to buffers 10' and 11'. Buffers 10 and 11 are changed over to buffers 10' and 11' by register 3 and bit (n) of the character code is set to register 3. At this point of time, a total of 3/2n bits of buffers 10, 11 and 10' are selected by selector 4, added newly and sent as character code (3/2n bits) to character generating circuit 7. When bit (n) of the character code read out from address (A+1) and set to register 3 is "1", on the other hand, 3/2n bits are similarly sent from address (A+2) of memory buffer 2 to circuit 7. 2: memory buffer 1: memory address counter
COPYRIGHT: (C)1980,JPO&Japio
JP7284778A 1978-06-16 1978-06-16 Display unit Pending JPS55915A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7284778A JPS55915A (en) 1978-06-16 1978-06-16 Display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7284778A JPS55915A (en) 1978-06-16 1978-06-16 Display unit

Publications (1)

Publication Number Publication Date
JPS55915A true JPS55915A (en) 1980-01-07

Family

ID=13501177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7284778A Pending JPS55915A (en) 1978-06-16 1978-06-16 Display unit

Country Status (1)

Country Link
JP (1) JPS55915A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56137390A (en) * 1980-03-28 1981-10-27 Fujitsu Ltd Code converting circuit
JPS58213388A (en) * 1982-05-10 1983-12-12 ゼロツクス・コ−ポレ−シヨン Printer and character formatting

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56137390A (en) * 1980-03-28 1981-10-27 Fujitsu Ltd Code converting circuit
JPS5936265B2 (en) * 1980-03-28 1984-09-03 富士通株式会社 code conversion circuit
JPS58213388A (en) * 1982-05-10 1983-12-12 ゼロツクス・コ−ポレ−シヨン Printer and character formatting
JPH0417459B2 (en) * 1982-05-10 1992-03-26 Xerox Corp

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