JPS6065332A - Signal deciding circuit - Google Patents

Signal deciding circuit

Info

Publication number
JPS6065332A
JPS6065332A JP17267783A JP17267783A JPS6065332A JP S6065332 A JPS6065332 A JP S6065332A JP 17267783 A JP17267783 A JP 17267783A JP 17267783 A JP17267783 A JP 17267783A JP S6065332 A JPS6065332 A JP S6065332A
Authority
JP
Japan
Prior art keywords
signal
memory
bit
bits
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17267783A
Other languages
Japanese (ja)
Inventor
Isao Ishikura
功 石倉
Noriyuki Suzuki
規之 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ando Electric Co Ltd
Original Assignee
Ando Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric Co Ltd filed Critical Ando Electric Co Ltd
Priority to JP17267783A priority Critical patent/JPS6065332A/en
Publication of JPS6065332A publication Critical patent/JPS6065332A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02Comparing digital values

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To decide plural conditions at a time and with a simple circuit by using a memory which has an address input of the same number of bits as those of an input signal and delivers the data of >=1 bit. CONSTITUTION:An input signal 10 contains 4 bits, and a memory 1 has 16 addresses (=2<4>) with constitution of (16 addresses X 3 bits). For instance, the signal 10 has a bit pattern of 1001. In such a case, a deciding signal 11 is set at 0. While a deciding signal 12 is set at 1 when the signal 10 has bit patterns of 0000, 0010 and 1100. The signal 12 is set at 0 with other bit patterns. In addition, a deciding signal 13 is set at 1 when the bit patterns of the signal 10 are included within a range of 0010-1000. Otherwise, the signal 13 is set at 0. If these working conditions are set previously, the memory 1 uses the signal 10 as an address and delivers the contents of bits 1-3 in the form of deciding signals 11-13.

Description

【発明の詳細な説明】 (a) 発明の技術分野 この発明は、人力信号があらかじめ設定したビットバタ
ー7と一致するか、またはあらかじめ設定した範囲内も
しくは範囲外にあるかを同時に複数の条fI+に対して
判定し、人力信5Jか各設定ビットパターンと一致した
場合または設定範囲内にある場合に限りそれぞれの条(
’lに対応した判定信号を出力する信号判定回路につい
てのものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention provides a method for simultaneously determining whether a human input signal matches a preset bit butter 7, or is within or outside a preset range. The respective article (
This relates to a signal determination circuit that outputs a determination signal corresponding to 'l.

(b) 従来技術と問題点 従来の信号判定回路には、コンパレータを使用したもの
やメモリを使用したものなどがあるが、複数の条f’l
を同時に判定する場合は、条件の数たけ判定回路が必要
となり回路か複数になるという間層かある。
(b) Prior art and problems Conventional signal determination circuits include those that use comparators and those that use memory.
If the conditions are to be judged at the same time, as many judgment circuits as there are conditions are required, resulting in the need for multiple circuits.

(C) 発明の1」的 この発明は、複数のビットて17.+I成する人力信号
か、あらかじめ設定した1種類以−Lのビットバター7
のどれかと一致するかとうか、またばあらかしめ設定し
た範囲内にあるかどうかを判定する信−シ判九回路につ
いてのものであり、簡単な回路で同時に複数の判疋条(
’lを判定することかできるイ5弓判定回路を提供する
ものである。
(C) Aspect 1 of the Invention This invention is based on a plurality of bits. +I human power signal or one type or more set in advance -L bit butter 7
This is about a nine-signal circuit that determines whether the signal matches any of the conditions, or whether it is within a preset range.
The purpose of this invention is to provide an A5 bow determination circuit that can determine 'l.

(c) 発明の実施例 まず、この発明による実施例の(1力成図を第1図に示
す。
(c) Embodiment of the Invention First, FIG. 1 shows a power diagram of an embodiment of the invention.

第1図の10は人力信号であり、第1121では4ビッ
ト(111ν成の人力信−Jの場合を例小している。
10 in FIG. 1 is a human input signal, and 1121 is a 4-bit (111ν) human input signal-J.

メモリlは人力(、i 弓10をアドレスf1:tシと
し、)′ルスイ1.t;て指】1・しlこンf’i J
也のピノ11、ビ、ノド2、ピノ173の内容を、それ
ぞれ判疋イ、1弓11〜13表して出力する。
Memory l is manually operated (,i, bow 10 is at address f1:t,)'rusui1. t;te finger】1・shikon f'i J
The contents of Pino 11, Bi, Nodo 2, and Pino 173 are expressed and output as 11 to 13, respectively.

人カイ1.5;10は4ピノl−R1ン成なので、メモ
リ1には2’=I(iの番地をもつメーI:りを使用す
る。
Since the number 1.5;10 consists of 4 pins l-R1, memory 1 uses 2'=I(mail with address i).

この実施例では、■(3番地×33ヒツト描成のメモリ
を使用する。
In this embodiment, a memory (3 addresses x 33 hits) is used.

次に、具体例に、J、り第1図の動f′1わよび、メモ
リ1の各番地の内容を設定する方法を説明する。
Next, as a specific example, a method for setting the contents of each address in the memory 1, such as the movement f'1 in FIG. 1, will be explained.

具体例として、次に小ず条件の場合を考える。As a specific example, consider next the case of the small condition.

なお、メモリ1のアルレス14. I (:ii!I 
A小である。
In addition, Arres 14. of memory 1. I (:ii!I
It is A small.

(γ)人カイ1−j5じ10のピノ1バター/かrlo
olJのとき、判定414号11を「1」とする。それ
以外のピノ1パターンのときは、判定(、riじ11を
「0」にする。
(γ) Hitoshi 1-j 5ji 10 Pinot 1 Butter/Karlo
When olJ, determination 414 No. 11 is set to "1". For other Pino 1 patterns, determine (, set riji11 to "0".

(イ)人カイ1.弓10のピノ1パターンかroooo
J、rooloJ、rl+00Jのとき、判定信−シ1
2をrlJとする。それり外のピノ1パターンのときは
、判定(5号12を「0」とする。
(b) Person Kai 1. Bow 10 Pino 1 pattern?roooo
When J, rooloJ, rl+00J, judgment signal - S1
Let 2 be rlJ. In the case of Pino 1 pattern other than that, the judgment (No. 5 and 12 is set as "0".

(’/) 人力信号10のビットバター/かroolo
Jからrl、000Jの範囲に含まれるとき、判定信ぢ
13を「1」とする。この範囲に含Jれないときは、判
定信号13を「0」とする。
('/) Human power signal 10 bit butter/karoolo
When included in the range from J to rl, 000J, the judgment signal 13 is set to "1". If it is not within this range, the determination signal 13 is set to "0".

(1)の動イ′1条件から、入力(r:!;10のピノ
1パター7 r 1001 Jに文・j応するメモリ1
の!J番」也のビ;・l、]の内容を「1」とする。そ
れ以外の?I;地のピノ11の内容を「0」とする。
From the motion A′1 condition in (1), input (r:!; 10 Pino 1 pattern 7 r 1001 Memory 1 corresponding to sentence j
of! The content of the number J'ya's B;・l,] is set to "1". Excluding that? I; Set the content of ground pinot 11 to "0".

(イ)の動fi条件から、入力信−;10のピノlバタ
ー y rooooj、rool、OJ、rl+00J
に対応するメモリ1の0番」出、2番J也、Cイ五J也
のビット2の内容をそれぞれ「1」とする。それ以外の
番地のビット2の内容を「0」とする。
From the dynamic fi conditions in (a), the input signal -; 10 pinot l butter y rooooj, rool, OJ, rl+00J
The contents of bit 2 of memory No. 0, No. 2, and No. 5, J of memory 1 corresponding to 1 are each set to 1. The contents of bit 2 at other addresses are set to "0".

(・ン)の動(’を条イ′1から、人力信号10のピノ
1パターンr 0000 JとrooolJに文・j応
するメモリ1の0聞地と1聞地のビット丁3の内容をそ
れぞれ10」とLl ビットパター7 r00]OJか
らrloooJに対応する2番」1!lから8聞地のビ
ット3の内容をそれぞれ「1」とし、ビットバター7 
rloolJからr 1+11 Jに対応するE〕番゛
地から1・゛岳Jl!lのそれぞれピノ13の内容を「
0」とする。
(・n) motion (from ``1'', the contents of bit 3 at the 0th position and 1st position of memory 1 corresponding to the pinot 1 pattern r 0000 J and rooolJ of the human input signal 10) 10 respectively, and Ll bit pattern 7 r00] The content of bit 3 corresponding to rloooJ from OJ is 1!
rloolJ to r 1+11 J corresponding to E゛ address ゛ to 1゛dake Jl! The contents of each Pino 13 in l are ``
0".

す1の説明にJ、り設定したメー℃す1の内容を第2図
に小ず。
Please refer to the explanation for item 1.The contents of item 1 are shown in Figure 2.

((り発明の効果 この発明によれば、次のような効果かある。((Effect of invention According to this invention, there are the following effects.

(ア) (、E;Ciの種類のビットパターンを判定す
ることかできる。
(A) (, E; It is possible to determine the type of bit pattern of Ci.

(イ)複数の種類のビットパターンを同時に判定するこ
とかできる。
(b) Multiple types of bit patterns can be determined simultaneously.

(”ン)(1)と(イ)から、ビットバター/の1li
ii l川内、範囲外の判定をすることかできる。
(''n) From (1) and (a), 1li of bit butter/
ii Kawauchi, it is possible to judge out of range.

(1) メモリたけて構成することかてき、他にゲート
回路なとを心霊としljい。
(1) Memory storage and configuration, as well as gate circuits, etc., are considered to be ghosts.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明による実施例の17ii成図、第2図
はある?シ数の条(’lに対するメ(;す1の内1トの
・例を小ず図。 1・・・ メモリ、10・・・人カイ、:号、11〜1
3−−’I’ll’、i!イ1−;− 第1図 第2図
Figure 1 is a 17ii diagram of an embodiment according to this invention, and is there a diagram of Figure 2? A small diagram of an example of 1 of 1 for 'l. 1... Memory, 10... Person Kai, : No., 11-1
3--'I'll', i! I1-;- Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 1、 複数ビ)l)で11カ成する人力信号をγトレス
イ11弓としてメモリに入力し、前記人力信号か設定ビ
ットバター7と一′致したときに111f記メモリか出
力する信)じ判定回路において、 1111記人カイJi号のビット数と等しいビット数の
アドレス入力をもち、1ビツト以1のデータを出力する
メモリを備え、 前記人力信ぢを同時に1つ以」−の判定条f′1にJ、
って判定し、その結果を出力することを特徴とする信号
判定回路。
[Claims] 1. Input the human input signal consisting of 11 bits in plural bi) l) into the memory as the γ trace signal 11, and when the human input signal matches the set bit butter 7, the input signal in the memory 111f is input. The same judgment circuit that outputs the human power signal has an address input with a number of bits equal to the number of bits of the 1111 record KaiJi, and is equipped with a memory that outputs data of 1 bit or more, and outputs one or more of the human power signals at the same time. ”-J in the judgment criterion f′1,
A signal judgment circuit characterized in that it makes a judgment and outputs the result.
JP17267783A 1983-09-19 1983-09-19 Signal deciding circuit Pending JPS6065332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17267783A JPS6065332A (en) 1983-09-19 1983-09-19 Signal deciding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17267783A JPS6065332A (en) 1983-09-19 1983-09-19 Signal deciding circuit

Publications (1)

Publication Number Publication Date
JPS6065332A true JPS6065332A (en) 1985-04-15

Family

ID=15946317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17267783A Pending JPS6065332A (en) 1983-09-19 1983-09-19 Signal deciding circuit

Country Status (1)

Country Link
JP (1) JPS6065332A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6441005A (en) * 1987-08-07 1989-02-13 Fuji Electric Co Ltd Programmable controller
EP0387440A1 (en) * 1986-12-19 1990-09-19 DePaul, Albert Dennis Comparing data and a computer system therefor

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55121543A (en) * 1979-03-12 1980-09-18 Nec Corp Area decision circuit
JPS57749A (en) * 1980-06-02 1982-01-05 Iwatsu Electric Co Ltd Parallel data comparison system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55121543A (en) * 1979-03-12 1980-09-18 Nec Corp Area decision circuit
JPS57749A (en) * 1980-06-02 1982-01-05 Iwatsu Electric Co Ltd Parallel data comparison system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0387440A1 (en) * 1986-12-19 1990-09-19 DePaul, Albert Dennis Comparing data and a computer system therefor
JPS6441005A (en) * 1987-08-07 1989-02-13 Fuji Electric Co Ltd Programmable controller

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