JPS55118677A - Fabricating method of insulated gate type semiconductor non-volatile memory - Google Patents
Fabricating method of insulated gate type semiconductor non-volatile memoryInfo
- Publication number
- JPS55118677A JPS55118677A JP2587879A JP2587879A JPS55118677A JP S55118677 A JPS55118677 A JP S55118677A JP 2587879 A JP2587879 A JP 2587879A JP 2587879 A JP2587879 A JP 2587879A JP S55118677 A JPS55118677 A JP S55118677A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- phosphorus
- insulated gate
- oxide film
- volatile memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 6
- 229910052698 phosphorus Inorganic materials 0.000 abstract 6
- 239000011574 phosphorus Substances 0.000 abstract 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 239000011521 glass Substances 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To prevent mixture of phosphorus in an insulating gate when forming the gate in an insulated gate semiconductor non-volatile memory and prevent the memory retaining property from lowering by coating a gate treated with phosphorus and formed in phosphorus glass on the surface and a field oxide film a silicon nitride film. CONSTITUTION:After forming a source, a drain diffused layer 3, a channel stopper 4, and a gate silicon heat oxide film 5 of 1000-15000Angstrom thick, phosphorus is diffused in a diffused layer 6 at 700-800 deg.C for 3-5min, and then a silicon nitride film 7 is formed with 200-600Angstrom . Then, the portion forming a multilayer insulated gate is dry etched. Then, the film 7, and the films 5, 6 are removed, and a heat oxide film 8 is formed at 900-950 deg.C to form a multilayer insulated gate thereat. Thus, a gate formed with phosphorus in glass and a field oxide film are coated with a nitride film. Accordingly, it can prevent the memory retaining property from lowering by preventing the phosphorus from entering into the multilayer insulated gate oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2587879A JPS55118677A (en) | 1979-03-06 | 1979-03-06 | Fabricating method of insulated gate type semiconductor non-volatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2587879A JPS55118677A (en) | 1979-03-06 | 1979-03-06 | Fabricating method of insulated gate type semiconductor non-volatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55118677A true JPS55118677A (en) | 1980-09-11 |
| JPS6244699B2 JPS6244699B2 (en) | 1987-09-22 |
Family
ID=12178034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2587879A Granted JPS55118677A (en) | 1979-03-06 | 1979-03-06 | Fabricating method of insulated gate type semiconductor non-volatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55118677A (en) |
-
1979
- 1979-03-06 JP JP2587879A patent/JPS55118677A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6244699B2 (en) | 1987-09-22 |
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