JPS55109000A - Memory unit erasing system - Google Patents

Memory unit erasing system

Info

Publication number
JPS55109000A
JPS55109000A JP1678779A JP1678779A JPS55109000A JP S55109000 A JPS55109000 A JP S55109000A JP 1678779 A JP1678779 A JP 1678779A JP 1678779 A JP1678779 A JP 1678779A JP S55109000 A JPS55109000 A JP S55109000A
Authority
JP
Japan
Prior art keywords
memory
address
erase
circuit
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1678779A
Other languages
Japanese (ja)
Inventor
Toyohiko Otsutsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1678779A priority Critical patent/JPS55109000A/en
Publication of JPS55109000A publication Critical patent/JPS55109000A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it possible to erase partially memory contents to shorten the program re-read time, by providing an address select circuit in a CPU.
CONSTITUTION: The maximum address and the minimum address of the area which the user does not want to erase in main memory unit 2 are set to registers 5 and 6 respectively by switch 4 for address indication provided in CPU1, and memory erase button 3 is depressed. Address select circuit 7 does not apply a reset voltage only to memory elements of the area designated by registers 5 and 6. Then, the reset voltage is generated for addresses, which are not designated by circuit 7, from memory erase circuit 8, and memory contents of these addresses are erased.
COPYRIGHT: (C)1980,JPO&Japio
JP1678779A 1979-02-16 1979-02-16 Memory unit erasing system Pending JPS55109000A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1678779A JPS55109000A (en) 1979-02-16 1979-02-16 Memory unit erasing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1678779A JPS55109000A (en) 1979-02-16 1979-02-16 Memory unit erasing system

Publications (1)

Publication Number Publication Date
JPS55109000A true JPS55109000A (en) 1980-08-21

Family

ID=11925882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1678779A Pending JPS55109000A (en) 1979-02-16 1979-02-16 Memory unit erasing system

Country Status (1)

Country Link
JP (1) JPS55109000A (en)

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