JPS5631140A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5631140A
JPS5631140A JP10712879A JP10712879A JPS5631140A JP S5631140 A JPS5631140 A JP S5631140A JP 10712879 A JP10712879 A JP 10712879A JP 10712879 A JP10712879 A JP 10712879A JP S5631140 A JPS5631140 A JP S5631140A
Authority
JP
Japan
Prior art keywords
address
cpu11
memory device
order
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10712879A
Other languages
Japanese (ja)
Inventor
Hiroshi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10712879A priority Critical patent/JPS5631140A/en
Publication of JPS5631140A publication Critical patent/JPS5631140A/en
Pending legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)

Abstract

PURPOSE:To obtain an information processor with which the decoding of the program PG is difficult by the third person, by making the addressing order of the PG of the PG counter different from the reading order of the PG out of the memory device storing the PG. CONSTITUTION:When the information processor starts working, the multiplexer 21 is controlled by the control unit 19. And the operation of the CPU11 is discontinued by the switch signal 22. At the same time, the address signal is supplied from the unit 19 in the form of the address of the address converting memory device 18. And the unit 19 makes the device 18 store the irregular address converting rule. Then the signal 22 is switches so as to secure a selection for the address of the CPU11, and thus the stop mode of the CPU11 is cancelled. The CPU11 generates the address signal through the device 18 and then reads the instruction out of the PG memory device 12. The contents of the device 12 and the data memory device 13 are rearranged based on the converting rule stored in the device 18. And the address order of the PG counter in the CPU11 is different from the order of the PG read out of the device 12. Accordingly, the protection of the secret is secured for the PG.
JP10712879A 1979-08-24 1979-08-24 Information processor Pending JPS5631140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10712879A JPS5631140A (en) 1979-08-24 1979-08-24 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10712879A JPS5631140A (en) 1979-08-24 1979-08-24 Information processor

Publications (1)

Publication Number Publication Date
JPS5631140A true JPS5631140A (en) 1981-03-28

Family

ID=14451201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10712879A Pending JPS5631140A (en) 1979-08-24 1979-08-24 Information processor

Country Status (1)

Country Link
JP (1) JPS5631140A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59212953A (en) * 1983-05-18 1984-12-01 Panafacom Ltd Information processor
JPS6011931A (en) * 1983-06-30 1985-01-22 Fujitsu Ltd One-chip microcomputer
JPH01194045A (en) * 1988-01-29 1989-08-04 Nec Corp Cpu board with secrecy function
JPH01288944A (en) * 1988-05-17 1989-11-21 Nec Corp Cpu circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59212953A (en) * 1983-05-18 1984-12-01 Panafacom Ltd Information processor
JPS6011931A (en) * 1983-06-30 1985-01-22 Fujitsu Ltd One-chip microcomputer
JPS6313210B2 (en) * 1983-06-30 1988-03-24 Fujitsu Ltd
JPH01194045A (en) * 1988-01-29 1989-08-04 Nec Corp Cpu board with secrecy function
JPH01288944A (en) * 1988-05-17 1989-11-21 Nec Corp Cpu circuit

Similar Documents

Publication Publication Date Title
KR830006725A (en) Numerical Control Method
JPS5631140A (en) Information processor
JPS54117883A (en) Numerical control device
JPS577690A (en) Initial program loading system
JPS545351A (en) Control unit
JPS5464277A (en) Sequence controller
JPS5614359A (en) Operation log storing system
JPS55122299A (en) Memory unit
JPS5469035A (en) Magnetic bubble cassette memory
JPS5599652A (en) Microprogram control unit
JPS5616226A (en) System start system
JPS57162031A (en) Address stack control system
JPS54161858A (en) Decoding system for extended machine address instruction
JPS5614358A (en) Operation log storing system
JPS5492150A (en) Gathering system for status information
JPS5681490A (en) Week programmer
JPS57168304A (en) Arithmetic device
JPS5621258A (en) Failure storage system in central processing unit
JPS57199055A (en) Information processing device
JPS5613596A (en) Control system for shift type memory
JPS56132648A (en) Information processor
JPS57162199A (en) Scan out system
JPS5595161A (en) Mass storage controller with data protective function
JPS55123737A (en) Microprogram address control system
JPS55118160A (en) Program control unit possessing self-diagnosis function