JPS55107252A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55107252A
JPS55107252A JP1448479A JP1448479A JPS55107252A JP S55107252 A JPS55107252 A JP S55107252A JP 1448479 A JP1448479 A JP 1448479A JP 1448479 A JP1448479 A JP 1448479A JP S55107252 A JPS55107252 A JP S55107252A
Authority
JP
Japan
Prior art keywords
mounting part
wiring
projections
mold
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1448479A
Other languages
Japanese (ja)
Inventor
Tamotsu Sato
Satoshi Watakari
Noboru Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1448479A priority Critical patent/JPS55107252A/en
Publication of JPS55107252A publication Critical patent/JPS55107252A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the short circuit troubles of wiring by providing projections to leads which are connected with the element mounting part of a lead frame at positions near the surface of sealing resin projecting to the element side. CONSTITUTION:The tips of plural leads 11 are disposed near an element mounting part 12 and projections 19 are provided to the holding parts 13 on both sides of the element mounting part 12. The projections 19 which project to the element mounting surface side and are formed by pressing are made near resin sealed edges. After brazing and wiring 17 an element 14, this lead frame is put in a mold 15. If the projections 19 are set at the ends of the cavity 16 of the mold 15, they are pressed by the mold 15 and the mounting part 12 goes down, therefore, the wiring 17 does not contact the edge of the element 14 or the mounting part 12. Resin is injected in this state. By so constructing, the short-circuiting of wiring can be prevented by the small deformation of a part of the lead frame.
JP1448479A 1979-02-09 1979-02-09 Manufacture of semiconductor device Pending JPS55107252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1448479A JPS55107252A (en) 1979-02-09 1979-02-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1448479A JPS55107252A (en) 1979-02-09 1979-02-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55107252A true JPS55107252A (en) 1980-08-16

Family

ID=11862320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1448479A Pending JPS55107252A (en) 1979-02-09 1979-02-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55107252A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862246A (en) * 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
EP0378209A2 (en) * 1989-01-11 1990-07-18 Kabushiki Kaisha Toshiba Hybrid resin-sealed semiconductor device
CN112289765A (en) * 2020-12-24 2021-01-29 瑞能半导体科技股份有限公司 Semiconductor package device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862246A (en) * 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
EP0378209A2 (en) * 1989-01-11 1990-07-18 Kabushiki Kaisha Toshiba Hybrid resin-sealed semiconductor device
CN112289765A (en) * 2020-12-24 2021-01-29 瑞能半导体科技股份有限公司 Semiconductor package device
CN112289765B (en) * 2020-12-24 2021-04-20 瑞能半导体科技股份有限公司 Semiconductor package device

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